TMPR4925 datasheet(291/590 Pages) TOSHIBA

291 / 590 page

Chapter 10 PCI Controller

10-29

10.4.4

PCI Configuration 1 Register (PCICFG1)

0xD00C

The following fields correspond to the following registers.

BIST field

→ BIST Register of the PCI Configuration Space

Header Type field

→ Header Type Register in the PCI Configuration Space

Latency Timer field

→ Latency Timer Register of the PCI Configuration Space

Cache Line Size field

→ Cache Line Size Register of the PCI Configuration Space.

This register cannot be accessed when the PCI Controller is in the Satellite mode.

BISTC

Reserved

MFUNS

R/L

: Type

0x00

: Initial value

CLS

R/W

: Type

0x00

: Initial value

Bits

Mnemonic

Field Name

Description

BISTC

BIST Capable

BIST Capable (Fixed value: 0, R)

Indicates that the BIST function is not being supported.

30:24



Reserved



MFUNS

Multi-Function

Multi-Function (Fixed value: 0, R)

0: Indicates that the device is a single-function device.

22:16

Header Type

Header Type (Initial value: 0x00, R/L)

Indicates the Header type.

0000000: Header Type 0

It is possible to change to the value that was written to the PCICDATA3 Register

when PCICCFG.LCFG is “1”.

15:8

Latency Timer

Latency Timer (Initial value: 0x00, R/W)

Sets the latency timer value. Specifies the PCI Bus clock count during which to abort

access when the GNT* signal is deasserted during PCI access. Since the lower two

bits are fixed to “0”, cycle counts can only be specified in multiples of 4.

7:0

CLS

Cache Line Size

Cache Line Size (Initial value: 0x00, R/W)

Is used to select the PCI Bus command during a Burst Read transaction. See “10.3.3

Supported PCI Bus Commands)” for more information.

Figure 10.4.4 PCI Configuration 1 Register

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