TMPR4925 datasheet(288/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-26

10.4.2

PCI Status, Command Register (PCISTATUS) 0xD004

The upper 16 bits correspond to the Status Register in the PCI Configuration Space, and the lower 16

bits correspond to the Command Register in the PCI Configuration Space.

This register cannot be accessed when in the Satellite mode. However, it is possible to read some

values of the upper 16 bits from the Satellite Mode PCI Status Register (PCISSTATUS).

DPE

SSE

RMA

RTA

STA

MDPE FBBCP Reserved 66MCP

Reserved

R/W1C R/W1C R/W1C R/W1C R/W1C

R/W1C

: Type

: Initial value

987

3210

Reserved

FBBEN SEREN STPC PEREN VPS MWIEN

MEMSP

IOSP

R/W

R/W : Type

0000

0/1

: Default

Bits

Mnemonic

Field Name

Explanation

DPE

Detected Parity

Error

Detected Parity Error (Initial value: 0, R/W1C)

Indicates that a parity error was detected. A parity error is detected in the three

following situations:

• Detected a data parity error as the Read command PCI initiator.

• Detected a data parity error as the Write command PCI target.

• Detected an address parity error.

This bit is set regardless of the setting of the Parity Error Response bit

(PCISTATUS.PEREN) of the PCI Status, Command Register.

1: Detected a parity error.

0: Did not detect a parity error.

SSE

Signaled System

Error

Signaled System Error (Initial value: 0, R/W1C)

Detects either an address parity error or a special cycle data parity error. This bit is

set when the SERR* signal is asserted.

1: Asserted the SERR* signal

0: Did not assert the SERR* signal.

RMA

Received Master

Abort

Received Master Abort (Initial value: 0, R/W1C)

This bit is set when a Master Abort aborts a PCI Bus Transaction when the PCI

Controller operates as the PCI initiator (except for special cycles).

1: Transaction was aborted by a Master Abort.

0: Transaction was not aborted by a Master Abort.

RTA

Received Target

Abort

Received Target Abort (Initial value: 0, R/W1C)

This bit is set when a Target Abort aborts a PCI Bus Transaction when the PCI

Controller operates as the PCI initiator.

1: Transaction was aborted by a Target Abort.

0: Transaction was not aborted by a Target Abort.

STA

Signaled Target

Abort

Signaled Target Abort (Initial value: 0, R/W1C)

This bit is set when a Target Abort aborts a PCI Bus Transaction when the PCI

Controller operates as the PCI target.

1: Bus transaction was aborted by a Target Abort.

0: Bus transaction was not aborted by a Target Abort.

26:25

DEVSEL Timing

DEVSEL Timing (Fixed value: 01, R)

Three DEVSEL assert timings are defined in the PCI 2.2 Specifications: 00b = Fast;

01b = Medium; 10b = Slow; 11b = Reserved).

With the exception of Read Configuration and Write Configuration, when the PCI

Controller is the PCI target, the DEVSEL signal is asserted to a certain bus

command and indicates the slowest speed for responding to the PCI Bus Master.

Figure 10.4.2 PCI Status, Command Register (1/2)

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