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TMPR4925 bảng dữ liệu(PDF) 171 Page - Toshiba Semiconductor |
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TMPR4925 bảng dữ liệu(HTML) 171 Page - Toshiba Semiconductor |
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171 / 590 page ![]() Chapter 8 DMA Controller 8-1 8. DMA Controller 8.1 Features The TX4925 contains a four-channel DMA Controller (DMAC) that executes DMA (Direct Memory Access) with memory and I/O devices. The DMA Controller has the following characteristics. • Has four on-chip DMA channels • Supports external I/O devices with 8-, 16-, and 32-bit Data Bus widths and transfer between memory devices. • Supports single address transfer (Fly-by DMA) and dual address transfer when in the external I/O DMA Transfer Mode that is operated by external request signals • Supports on-chip Serial I/O Controllers and AC-Link Controllers • Supports Memory-Memory Copy modes that do not have address boundary limitations. Burst transfer of up to eight words is possible for each Read or Write operation. • Supports Memory Fill mode that writes word data to the specified memory region • Supports Chained DMA Transfer • On-chip signed 24-bit address count up registers for both the source address and destination address • On-chip 26-bit Byte Count Register for each channel • One of two methods can be selected for determining access priority among multiple channels: Round Robin or Fixed Priority • Big Endian or Little Endian mode can be set separately for each channel |
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