S75WS256NDFBAWMB datasheet(215/216 Pages) SPANSION

215 / 216 page

February 17, 2005 S75WS-N-00_A0

S75WS256Nxx Based MCPs

213

Advance

Information

35.2.1

Extended Write Timing— Asynchronous Write Operation

Modified timings are required during extended Write operations (see Figure 35.3). An extended

Write operation requires that both the Write pulse width (tWP) and the data valid period (tDW) be

lengthened to at least the minimum Write cycle time (tWC [MIN]). These increased timings ensure

that time is available for both a refresh operation and a successful completion of the Write

operation.

35.3 Page Mode Read Operation

When a CellularRAM device is configured for page mode operation, the address inputs are used

to accelerate Read accesses and cannot be used by the on-chip circuitry to schedule refresh. If

CE# is Low longer than the tCEM maximum time of 4µs during a Read operation, the system must

allow tAA (not tAPA, as would otherwise be expected) for all subsequent intrapage accesses until

CE# goes High.

35.4 Burst-Mode Operation

When configured for burst-mode operation, it is necessary to allow the device to perform a refresh

within any 4µs window. One of two conditions will enable the device to schedule a refresh within

4µs. The first condition is when all burst operations complete within 4µs. A burst completes when

the CE# signal is registered High on a rising clock edge. The second condition that allows a refresh

is when a burst access crosses a row boundary. The row-boundary crossing causes Wait to be

asserted while the next row is accessed and enables the scheduling of refresh.

35.5 Summary

CellularRAM products are designed to ensure that any possible asynchronous timings do not

cause data corruption due to lack of refresh. Slow bus timings on asynchronous Write operations

require that tWP and tDW be lengthened. Slow bus timings during asynchronous page Read oper-

ations cause the next intrapage Read data to be delayed to tAA.

Burst mode timings must allow the device to perform a refresh within any 4µs period. A burst

operation must either complete (CE# registered High) or cross a row boundary within 4µs to en-

sure successful refresh scheduling. These timing requirements are likely to have little or no impact

when interfacing a CellularRAM device with a low-speed memory bus.

Figure 35.3 Extended Write Operation

tCEM or tTM > 4μs

tWP > tWC (MIN)

tDW > tWC (MIN)

ADDRESS

CE#

LB#/UB#

WE#

DATA-IN

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