S75WS256NDFBAWMB datasheet(214/216 Pages) SPANSION

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S75WS256Nxx Based MCPs

S75WS-N-00_A0 February 17, 2005

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Inf o rmation

35 How Extended Timings Impact CellularRAM™ Operation

35.1

Introduction

This section describes CellularRAM™ timing requirements in systems that perform extended

operations.

CellularRAM products use a DRAM technology that periodically requires refresh to ensure against

data corruption. CellularRAM devices include on-chip circuitry that performs the required refresh

in a manner that is completely transparent in systems with normal bus timings. The refresh cir-

cuitry imposes constraints on timings in systems that take longer than 4µs to complete an

operation. Write operations are affected if the device is configured for asynchronous operation.

Both Read and Write operations are affected if the device is configured for page or burst-mode

operation.

35.2 Asynchronous Write Operation

The timing parameters provided in Figure 34.4 require that all Write operations must be com-

pleted within 4µs. After completing a Write operation, the device must either enter standby (by

transitioning CE# High), or else perform a second operation (Read or Write) using a new address.

Figure 35.1 and Figure 35.2 demonstrate these constraints as they apply during an asynchronous

(page-mode-disabled) operation. Either the CE# active period (tCEM in Figure 35.1) or the ad-

dress valid period (tTM in Figure 35.2) must be less than 4µs during any Write operation,

otherwise, the extended Write timings must be used.

Figure 35.1 Extended Timing for tCEM

Figure 35.2 Extended Timing for tTM

Table 35.1 Extended Cycle Impact on Read and Write Cycles

Page Mode

Timing Constraint

Read Cycle

Write Cycle

Asynchronous

Page Mode Disabled

tCEM and tTM > 4µs

(See Figure 35.1 and

Figure 35.2.)

No impact.

Must use extended Write

timing.

(See Figure 35.2)

Asynchronous

Page Mode Enabled

tCEM > 4µs

(See Figure 35.1.)

All following intrapage Read

access times are tAA (not tAPA).

Must use extended Write

timing.

(See Figure 35.3)

Burst

tCEM > 4µs (See Figure 35.1.)

Burst must cross a row boundary within 4µs.

CE#

ADDRESS

tCEM

4 μs

CE#

ADDRESS

TM<

4μs

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