S75WS256NDFBAWMB datasheet(175/216 Pages) SPANSION

175 / 216 page

February 17, 2005 S75WS-N-00_A0

S75WS256Nxx Based MCPs

173

Advance

Information

Notes:

1. See How Extended Timings Impact CellularRAM™ Operation below.

2. Low-Z to High-Z timings are tested with the circuit shown in Figure 34.2. The High-Z timings measure a 100mV transition from either VOH

or VOL toward VCCQ/2.

3. High-Z to Low-Z timings are tested with the circuit shown in Figure 34.2. The Low-Z timings measure a 100mV transition away from the

High-Z (VCCQ/2) level toward either VOH or VOL.

Table 34.4 Asynchronous Write Cycle Timing Requirements

Parameter

Symbol

70 ns/80 MHz

85 ns/66 MHz

Units

Notes

Min

Max

Min

Max

Address and ADV# Low Setup Time

tAS

Address Hold from ADV# Going High

tAVH

Address Setup to ADV# Going High

tAVS

Address Valid to End of Write

tAW

LB#/UB# Select to End of Write

tBW

Maximum CE# Pulse Width

tCEM

µs

CE# Low to Wait Valid

tCEW

7.5

Async Address-to-Burst Transition Time

tCKA

CE# Low to ADV# High

tCVS

Chip Enable to End of Write

tCW

Data Hold from Write Time

tDH

Data Write Setup Time

tDW

Chip Disable to Wait High-Z Output

tHZ

Chip Enable to Low-Z Output

tLZ

End Write to Low-Z Output

tOW

ADV# Pulse Width

tVP

ADV# Pulse Width High

tVPH

ADV# Setup to End of Write

tVS

Write Cycle Time

tWC

Write to DQ High-Z Output

tWHZ

Write Pulse Width

tWP

Write Pulse Width High

tWPH

Write Recovery Time

tWR

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