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February 17, 2005 S75WS-N-00_A0
S75WS256Nxx Based MCPs
171
Advance
Information
Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. See How Extended Timings Impact CellularRAM™ Operation below.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 34.2. The Low-Z timings measure a
4. 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
5. Low-Z to High-Z timings are tested with the circuit shown in Figure 34.2. The High-Z timings measure a 100mV transition from either VOH
or VOL toward VCCQ/2.
Table 34.2 Asynchronous Read Cycle Timing Requirements
Parameter
Symbol
85ns/66 MHz
70ns/80 MHz
Units
Notes
Min
Max
Min
Max
Address Access Time
tAA
85
70
ns
ADV# Access Time
tAADV
85
70
ns
Page Access Time
tAPA
25
20
ns
Address Hold from ADV# High
tAVH
55
ns
Address Setup to ADV# High
tAVS
10
10
ns
LB#/UB# Access Time
tBA
85
70
ns
LB#/UB# Disable to DQ High-Z Output
tBHZ
88
ns
4
LB#/UB# Enable to Low-Z Output
tBLZ
10
10
ns
3
CE# High between Subsequent Mixed-Mode Operations
tCBPH
55
ns
Maximum CE# Pulse Width
tCEM
44
µs
2
CE# Low to Wait Valid
tCEW
1
7.517.5
ns
Chip Select Access Time
tCO
85
70
ns
CE# Low to ADV# High
tCVS
10
10
ns
Chip Disable to DQ and Wait High-Z Output
tHZ
88
ns
4
Chip Enable to Low-Z Output
tLZ
10
10
ns
3
Output Enable to Valid Output
tOE
20
20
ns
Output Hold from Address Change
tOH
55
ns
Output Disable to DQ High-Z Output
tOHZ
88
ns
4
Output Enable to Low-Z Output
tOLZ
55
ns
3
Page Cycle Time
tPC
25
20
ns
Read Cycle Time
tRC
85
70
ns
ADV# Pulse Width Low
tVP
10
10
ns
ADV# Pulse Width High
tVPH
10
10
ns



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