S75WS256NDFBAWMB datasheet(165/216 Pages) SPANSION

165 / 216 page

February 17, 2005 S75WS-N-00_A0

S75WS256Nxx Based MCPs

163

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Information

31.2.6

Latency Counter (BCR[13:11]): Default = Three-Clock Latency

The latency counter bits determine how many clocks occur between the beginning of a Read or

Write operation and the first data value transferred. Latency codes from two (three clocks) to six

(seven clocks) are allowed (see Table 31.4 and Figure 31.6 below).

Note: Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is trans-

ferred on the next clock cycle.

Note: Non-default BCR setting: Wait active Low.

Figure 31.5 Wait Configuration During Burst Operation

Table 31.4 Variable Latency Configuration Codes

BCR[13:11]

Latency Configuration

Code

Latency (Note)

Max Input Clk Frequency (MHz)

Normal

Refresh Collision

70 ns/80 MHz

85 ns/66 MHz

010

2 (3 clocks)

75 (13.0 ns)

44 (22.7 ns)

011

3 (4 clocks)—default

80 (12.5 ns)

66 (15.2 ns)

100

4 (5 clocks)

Figure 31.6 Latency Counter (Variable Initial Latency, No Refresh Collision)

D[0]

D[1]

D[2]

D[3]

D[4]

CLK

WAIT

DQ[15:0]

BCR[8] = 0

DATA VALID IN CURRENT CYCLE

BCR[8] = 1

DATA VALID IN NEXT CYCLE

Don't care

Legend:

Code 2

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid Address

Valid

Output

Code 3

(Default)

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Code 4

Valid

Output

Valid

Output

Valid

Output

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

VOH

VOL

CLK

A[21:0]

ADV#

A/DQ[15:0]

Don't care

Undefined

Legend:

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