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MPC821 bảng dữ liệu(PDF) 187 Page - NXP Semiconductors

tên linh kiện MPC821
Giải thích chi tiết về linh kiện  Design Specification
PDF  242 Pages
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MPC821 bảng dữ liệu(HTML) 187 Page - NXP Semiconductors

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Functional Description
MOTOROLA
MPC860TFADS Daughter Board Design Specification—Rev 0.1
11
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
4 - Functional Description
In this chapter the various modules combining the MPC860TFADSDB are described to their design
details.
4•1
Reset & Reset - Configuration
There are 3 reset sources for the MPC:
1) Power-On ResetA
2) Hard Reset
3) Soft Reset
4•1•1
Power-On Reset
The Power - On Reset on the MPC860T-FADSB is generated out of 2 alternative power buses:
1)
The keep alive power bus
2)
The MAIN power bus.
Selection between the 2 options is done by means of jumper.
When option (1) above is selected, the power-on reset is generated by a dedicated voltage detector
made by Seiko the S-8051HN-CD-X with detection voltage range of 1.795 to 2.005V. During keep
alive power-on or when there is a voltage drop of that input into the above range Power-On Reset is
generated, i.e., PORESET* input of the MPC is asserted for a period of approximately 4 sec.
When option (2) above is selected, the power-on reset is generated by a dedicated voltage detector
made
by Seiko the S-8052ANY-NH-X with detection voltage range of 2.595V to 2.805V. During MAIN 3.3V
bus power-on or when there is a voltage drop of that input into the above range Power-On Reset is
generated, i.e., PORESET* input of the MPC is asserted for a period of approximately 4 sec. The
MAIN power on reset also generates power-on reset to all logic located on the motherboard.
When PORESET* is asserted to the MPC, the Power-On reset configuration is made available to
MPC. See 4•1•6•1 "Power - On Reset Configuration" on page 29 of MPC8XXFADS User’s Manual.
4•1•2
Hard Reset
Hard Reset is generated to the MPC860T by the following sources:
1)
The MAIN power-on reset
2)
Manual Hard Reset generated on the mother board
3)
The debug port Hard reset
4)
and by MPC860T’s internal sources.
When the open-drain signal Hard Reset is asserted, Hard reset configuration is driven on the data
bus by logic on the motherboard. See 4•1•6•2 "Hard Reset Configuration" on page 29 on
MPC8XXFADS User’s Manual.
4•1•3
Soft Reset
Soft Reset is generated to the MPC860T by the following sources:
1)
The debug port controller located on the motherboard
2)
Manual Soft Reset generated on the motherboard
A. In fact generated on the daughter board.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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