DSP56307SLASHD datasheet(4/156 Pages) MOTOROLA

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DSP56307 Technical Data

MOTOROLA

DSP56307

Features

Enhanced Filtering Coprocessor (EFCOP)

The on-chip filtering and echo-cancellation coprocessor runs in parallel to the DSP core.

On-Chip Memories

64 K on-chip RAM total

Program RAM, Instruction Cache, X data RAM, and Y data RAM size is programmable:

192 x 24-bit bootstrap ROM

Off-Chip Memory Expansion

Data memory expansion to two 256K

× 24-bit word memory spaces (or up to two

4 M

× 24-bit word memory spaces by using the address attribute AA0ÐAA3 signals)

Program memory expansion to one 256K

× 24-bit words memory space (or up to one

4 M

× 24-bit word memory space by using the address attribute AA0ÐAA3 signals)

External memory expansion port

Chip Select Logic for glueless interface to static random access memory (SRAMs)

On-chip DRAM Controller for glueless interface to dynamic random access memory

(DRAMs)

Program RAM

Size

Instruction

Cache Size

X Data RAM

Size*

Y Data RAM

Size*

Instruction

Cache

Switch

Mode

MSW1 MSW0

16K

× 24-bit

24K

× 24-bit

24K

× 24-bit

disabled

0/1

1 K

× 24-bit

1024

× 24-bit

24K

× 24-bit

24K

× 24-bit

enabled

disabled

0/1

48K

× 24-bit

disabled

enabled

47K

× 24-bit

1024

× 24-bit

enabled

40K

× 24-bit

12K

× 24-bit

12K

× 24-bit

disabled

enabled

39K

× 24-bit

1024

× 24-bit

12K

× 24-bit

12K

× 24-bit

enabled

32K

× 24-bit

16K

× 24-bit

16K

× 24-bit

disabled

enabled

31K

× 24-bit

1024

× 24-bit

16K

× 24-bit

16K

× 24-bit

enabled

24K

× 24-bit

20K

× 24-bit

20K

× 24-bit

disabled

enabled

23K

× 24-bit

1024

× 24-bit

20K

× 24-bit

20K

× 24-bit

enabled

*Includes 4K

× 24-bit shared memory (i.e., memory shared by the core and the EFCOP)

Not Recommended for New Design

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