S32K310 datasheet(130/137 Pages) NXP

130 / 137 page

Rev 3, Oct 2021

— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=0, Capacitance=25pF" Min changed from "1.1" to "0.5"

— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=0, Capacitance=25pF" Max changed from "7.0" to "4"

— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=1, Capacitance=25pF" Min changed from "2.6" to "2.1"

— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=1, Capacitance=25pF" Max changed from "11.0" to "9"

— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=0, Capacitance=25pF" Min changed from "0.8" to "0.4"

— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=0, Capacitance=25pF" Max changed from "3.4" to "2"

— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=1, Capacitance=25pF" Min changed from "1.5" to "1.2"

— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=1, Capacitance=25pF" Max changed from "7.8" to "6.4"

— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=0, Capacitance=50pF" Min changed from "2.5" to "1.1"

— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=0, Capacitance=50pF" Max changed from "10.8" to "7"

— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=1, Capacitance=50pF" Min changed from "3.6" to "2.6"

— for Symbol "TR_TF_33_F" with condition "DSE=0, SRE=1, Capacitance=50pF" Max changed from "15.0" to "11"

— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=0, Capacitance=50pF" Min changed from "1.5" to "0.8"

— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=0, Capacitance=50pF" Max changed from "5.5" to "4.2"

— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=1, Capacitance=50pF" Min changed from "2.2" to "1.5"

— for Symbol "TR_TF_33_F" with condition "DSE=1, SRE=1, Capacitance=50pF" Max changed from "10.0" to "7.8"

• In section "SAR ADC", added paragraph "All below specs are applicable when only one ADC instance is in operation .....

to determine the most appropriate settings for AVGS." and removed footnote from RS specification.

• In section "SAR ADC", added specifications for CP1, CP2 and RSW1 corresponding to all channels, shared channels

and precision channels. Also added the related figure.

• In section "PLL", removed some non-applicable footnotes.

• In section "LPSPI", added information before the table The Low Power Serial Peripheral Interface (LPSPI) provides a

synchronous serial bus with master....".

• In section "LPSPI0 20 MHz and 15 MHz Combinations", added note as "Trace length should not exceed 11 inches for

SCK pad when used in Master loopback mode."

• Added "I3C" specifications.

• In section "Ethernet MII (100 Mbps)", for "RXCLK frequency" typ value moved to max.

• In section "Ethernet RMII", added paragraph "The following timing specs are defined at the device I/O pin and must

be .....I/O operating voltage ranges from 2.97 V to 3.63 V."

• In section "QuadSPI Quad 3.3V SDR 120MHz", for Symbol "tSDC" footnote added "For S32K342 100MQFP, tSDC spec

would be ..."

• In section "QuadSPI Quad 3.3V SDR 120MHz" added sentence "Program register value

QuadSPI_DLLCRA[SLV_FINE_OFFSET] to 4'b0001.".

• In section "QuadSPI Octal 3.3V DDR 120MHz", Symbol "tSCK" min is calrified, condition updated to External DQS and

"tSCK" with condition Internal Loopback is deleted.

• In section "QuadSPI Octal 3.3V DDR 120MHz", Symbol "tSDC" condition updated to External DQS and "tSDC" with

condition Internal Loopback is deleted..

• In section "QuadSPI Octal 3.3V DDR 120MHz", specifications tISU_PCS, tIH_PCS, tCK2CKmin and tCK2CKmax are

deleted.

NXP Semiconductors

Revision history

S32K3xx Data Sheet, Rev. 5.2, 10/2022

Data Sheet: Technical Data

Preliminary Information

130 / 137

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