MEC1632 datasheet(112/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 112

 2012-2018 Microchip Technology Inc.

7.4.10.2

EC Controlled Dynamic Power States

Table 7-14 illustrates the EC Controlled Dynamic Power States that can be achieved using the clock gating feature of

Power Management Interface. The EC Controlled Dynamic Power States closely mirror the system power states

defined by the Generic Block Clocking Model, but 1) redefine the “preparing to sleep” state to include the affects of the

EC sleep state, 2) define additional implementation-specific sleep states that affect Wake Interface latency and 3) indi-

cate the aggregated response of all the MEC1632 power-managed blocks. Typically, the higher the state number in

Table 7-14. the greater the system power savings. Traversing the EC Controlled Dynamic Power States requires the

SLEEP_FLAG, ARC_CLK_DISABLE signal, WAKE signal, the SLEEP CONFIG field, the Block Sleep Enable Registers

and the Clock Required Status Registers.

TABLE 7-14:

EC CONTROLLED DYNAMIC POWER STATES

Power

State Name

SLEEP_FLAG

(

Note 7-20)

ARC_CLK_

DISABLE

(

Note 7-21)

Global

Block

Clock

Status

(

Note 7-22)

SLEEP

CONFIG

(

Note 7-23)

Description

FULL

POWER

The system is running. This is the

highest power consumption state.

EC SLEEP

EC has executed a sleep

instruction. The rest of the system is

unaffected by the EC SLEEP state.

PREPARING

SYSTEM

SLEEP

Sleep commands issued to all sleep-

enabled blocks (see "EC Controlled

Sleep State Activation," on

page 117). The EC can return to the

FULL POWER state from PREPARING

SYSTEM SLEEP by de-asserting (‘0’)

SLEEP_FLAG (see also Note 7-24).

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