MEC1632 datasheet(61/636 Pages) MICROCHIP

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DS00001592B-page 61

MEC1632

4.4

AHB Buses

Addresses and internal buses in the MEC1632 are compatible with ARM Limited’s Advanced Microprocessor Bus Archi-

tecture

(AMBA), as specified in AMBA

™ Specification (Rev 2.0), 1999.

As seen in FIGURE 4-1: MEC1632 Bus Hierarchy on page 56, there are two separate AHB buses, the EC AHB and the

Host AHB. The first has one master, the EC, and two slaves, while the second has two masters, the LPC interface and

the AHB-AHB bridge, and four slaves. The bus connections are summarized in Table 4-4, "MEC1632 AHB Buses" and

can be seen in Figure 4-1.

The AHB-to-AHB bridge is a one-way device: addresses generated on the EC AHB can be propagated to the Host AHB

bus, but addresses on the Host AHB bus cannot be propagated to the EC AHB bus. This is the reason that the Host is

restricted from accessing the address range F0_0000h to F0_FFFFh (the address range of the EC SPB bridge). The

bridge maps address from FD_0000h through FF_FFFFh. Multi-word block transfers on the EC AHB are converted by

the bridge into a series of sequential 4-byte transfers.

Both the EC and the LPC interface can have at most one outstanding AHB bus request at one time. On the Host AHB,

the LPC interface always has priority over the AHB-AHB bridge. Both AHB buses support byte, halfword and word AHB

transfers. The only Burst mode supported on the EC AHB is an incrementing burst of 4 beats of 4 bytes per beat. Burst

mode is not supported on the Host AHB. AHB bus locking or early burst termination are not supported.

4.4.1

BUS CLOCKING

The Host AHB runs at the MEC1632 system clock rate (MCLK). The bus clock and the bus arbiter will be shut down

when there are no transactions active on the bus. The bus clock and arbiter will be restarted as soon as an address

is acquired from the LPC bus, or when an EC AHB bus transaction is mapped, via the AHB-to-AHB bridge, to the

address space of the Host AHB. The EC AHB clock can be programmed to run at any of the available rates as defined

by Block Sleep Enable Registers (see Section 7.8.4, "Block Sleep Enable Registers," on page 136). The EC bus clock

is shut down when the EC is idle.

If the Host AHB clock is idle when an LPC transaction arrives at the LPC interface, the LPC interface will restart the AHB

bus clock and arbiter early enough so that as soon as an I/O address is translated to an AHB address the I/O transaction

can be placed on the AHB without delay. If the I/O address is not claimed by the MEC1632 then the LPC interface will

drop its bus request. If the EC is not requesting the Host AHB at the same time, the Host AHB bus clock will again

shut down.

4.4.2

ADDRESS FRAMING

The EC can directly address all peripherals on the MEC1632. The Host, by contrast, is restricted in what it can address.

The Host accesses the MEC1632 through the LPC bus, using I/O cycles, Memory Cycles and Firmware Hub cycles

(see Section 6.0, "Host Interface," on page 79). These cycles are mapped into the MEC1632 address space accessible

by the LPC interface.

The mapping function forces some of the address bits to preset values, as shown in Table 4-5, "LPC to MEC1632

Address Mapping". This mapping has the effect of creating four contiguous 256-byte regions: LPC I/O, EC-only, LPC

DMA and LPC Configuration. Together, the four regions create a 1024 byte “frame” for each logical device that is acces-

sible to the Host. There is therefore a maximum of 64 Logical Devices, each with a 1KB frame.

LPC I/O cycles for Runtime Registers are mapped into the first 256 bytes of the 1024 byte frame. Configuration Regis-

ters, which are accessed through a Configuration portal typically located at addresses 2Eh and 2Fh in the LPC I/O

space, are restricted to the highest 256 bytes of the 1024 byte frame.

DMA FIFO addresses are restricted to offsets between 200h and 2FFh within a Logical Device frame. In addition, DMA

FIFO addresses are restricted to 32-bit aligned addresses, that is, address bits [1:0] are both 0. The low 10 bits of a

DMA FIFO are thus in the form ‘10xxxxxx00b’.

TABLE 4-4:

MEC1632 AHB BUSES

AHB Bus

Master Interfaces

Slave Interfaces

EC AHB

EC SPB bridge

AHB-AHB bridge

Host AHB

LPC Interface

AHB-AHB bridge

LPC SPB bridge

SPI bridge

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