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MEC1632 bảng dữ liệu(PDF) 15 Page - Microchip Technology

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MEC1632 bảng dữ liệu(HTML) 15 Page - Microchip Technology

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 2012-2018 Microchip Technology Inc.
DS00001592B-page 15
MEC1632
3.4
General System/Layout Issues
3.4.1
PIN DEFAULT STATE THROUGH POWER TRANSITIONS
The power state and power state transitions illustrated in Table 3-2 are defined in , . Pin behavior in this table assumes
no specific programming to change the pin state. All GPIO default pins have the same behavior described in Table 3-
2 as generically as GPIOXXX.
TABLE 3-2:
Pin Default State Through Power Transitions
Signal
VBAT
applied
VBAT
STABLE
VTR
applied
nSYS
_RST de-
asserted
VCC_
PWRGD
asserted
VCC_
PWRGD
de-
asserted
nSYS_
RST
asserted
VTR un-
powered
VBAT un-
powered
Notes
GPIO042
unpowered unpowered
low
In
In
In
Z
glitch
unpowered
GPIO043
unpowered unpowered
low
In
In
In
Z
glitch
unpowered
GPIO062
unpowered unpowered
low
Out=0
Out
Out
Out
glitch
unpowered
GPIOXXX
unpowered unpowered
Z
In
In
In
Z
glitch
unpowered Note E
SER_IRQ
unpowered unpowered
glitch
In
Z>I/O (P) >Z
In
In
glitch
unpowered Note A
LRESET#
unpowered unpowered
glitch
In
In
In
Z
glitch
unpowered Note A
PCI_CLK
unpowered unpowered
glitch
In
In
In
Z
glitch
unpowered
LFRAME#
unpowered unpowered
glitch
In
In
In
Z
glitch
unpowered
LAD0
unpowered unpowered
glitch
In
In>I/O (P) >In
In
Z
glitch
unpowered
LAD1
unpowered unpowered
glitch
In
In>I/O (P) >In
In
Z
glitch
unpowered
LAD2
unpowered unpowered
glitch
In
In>I/O (P) >In
In
Z
glitch
unpowered
LAD3
unpowered unpowered
glitch
In
In>I/O (P) >In
In
Z
glitch
unpowered
CLKRUN#
unpowered unpowered
glitch
In
Z>I/O (P) >Z
In
Z
glitch
unpowered
BGPO0
Out=0
Out=0
Retain
Retain
Retain
Retain
Retain
Retain
unpowered Note B
VCI_INx#
In
In
In
In
In
In
In
In
unpowered
VCI_OUT
Out logic
Out logic
Out logic
Out logic
Out logic
Out logic
Out logic
Out logic
unpowered Note C
VCI_OVRD_IN
In
In
In
In
In
In
In
In
unpowered
XTAL1
Crystal In
Crystal In
Crystal In Crystal In
Crystal In
Crystal In Crystal In Crystal In
Crystal In
XTAL2
Crystal Out Crystal Out
Crystal
Out
Crystal
Out
Crystal Out
Crystal
Out
Crystal
Out
Crystal
Out
Crystal Out
Legend
Notes
Note A:
Note B:
Z = Tristate
Note C:
Note D:
Note E:
Does not include GPIO042, GPIO043, and GPIO062
(P) = I/O state is driven by protocol while
power is applied.
Pin exhibits "VCC" power domain emulation.
Pin is programmable by the EC and retains its value through a VTR power cycle.
Pin is programmable by the EC and affected by other VBAT inputs pins.
Pin exhibits "VTR" power domain emulation.



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