MEC1632 datasheet(100/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 100

 2012-2018 Microchip Technology Inc.

Note 7-3

there is accuracy adjustment latency as described in Section 7.4.3, "20 MHz Oscillator," on

page 100.The 20 MHz Oscillator can be disabled using the Power Management Interface.

Note 7-4

this depends on the XTL_SEL bit in the Clock Enable Register.

Note 7-5

an external single-ended 32.768 KHz clock source may be VTR or VBAT powered. Note that higher

than normal VBAT current may occur when VTR transitions from unpowered to powered if the

switching threshold on the external single-ended 32.768 KHz clock source is different than the

internal Power Mux switch threshold.

7.4.3

20 MHZ OSCILLATOR

The MEC1632 Clock Generator includes a high-accuracy, low power, low start-up latency 20 MHz Oscillator.The 20

MHz Oscillator is always enabled except during power up and in the SYSTEM HEAVY SLEEP 3 and SYSTEM DEEP-

EST SLEEP state when the oscillator is stopped by hardware as described in Section 7.4.10, "Power Management Inter-

face," on page 111.The 20 MHz Oscillator timing parameters are shown in Table 7-6.

The 20 MHz Oscillator is reset by VTRGD as described in Section 7.6, "Reset Interface," on page 124 and powered by

a dedicated voltage regulator and power cycled as described in Section 7.4.10.6, "Wake Interface," on page 118.

FIGURE 7-2:

20 MHz Oscillator BLOCK DIAGRAM

FIGURE 7-3:

20 MHz Oscillator LOCK TIME

nPWRDN

START

fOUT

nPWRDN

START

tSTART

fOUT

tPULSE

fOSC

FREQ LOCK

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