MEC1632 datasheet(31/636 Pages) MICROCHIP

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DS00001592B-page 31

MEC1632

3.6.2.2

MUX

If the pin has an associated GPIO, then the MUX column refers to the Mux Control field in the GPIO Pin Control Register.

Setting the Mux Control field to value listed in the row will configure the pin for the signal listed in the Signal column on

the same row. The row marked “Default” is the setting that is assigned on system reset.

If there is no GPIO associated with a pin, then the pin has a single function.

3.6.2.3

Signal

This column lists the signals that can appear on each pin, as configured by the MUX control.

3.6.2.4

Buffer Type

Pin buffer types are defined in Table 45-4, “DC Electrical Characteristics,” on page 604.

GPIO pins with the (I/O/OD) buffer type are configurable to operate as an I, an IO, or an IOD type buffer. The user may

use this GPIO signal as an input only, an output only, or an I/O pin. Following the closing parenthesis is a value

expressed in terms of mA, which indicates the output drive strength when the pin is configured as a buffer of type O or

OD. The buffer is configured by the Output Buffer Type field in the GPIO Pin Control Register.

For signals that are multiplexed with GPIOs the following rules apply

• Buffer Type Notation (O/OD)-mA. Output buffer configuration options are programmed in the GPIO Pin Control

• All other Buffer Type Notations. The buffer configuration is controlled by the logic driving the signal. When the

GPIO mux control is configured for these signals, the Output Buffer Type field must be configured for Push-Pull.

3.6.2.5

Signal Power Well

This column defines the power well that powers the pin.

3.6.2.6

Emulated Power Well

For GPIOs, the emulated power well is defined by the Power Gating Signals field in the GPIO Pin Control Register. All

GPIOs can be configured for VCC power well emulation, as defined in Section 3.6.1, "VCC Power Domain Emulation".

Power well emulation for signals that are multiplexed with GPIO signals is controlled by the GPIO Power Gating config-

uration. Entries for these signals in the following tables represent typical applications.

Power well emulating for signals that are not multiplexed with GPIO signals is defined by the entries in this column.

When VCC_PWRGD is low outputs for these signals are tri-stated; internal values for these signals are gated according

to the entries in the Gated State column.

3.6.2.7

Gated State

This column defines the internal value of a signal when either its emulated power well is inactive or it is not selected by

the GPIO alternate function multiplexor. A value of “No Gate” means that the internal signal always follows the pin even

when the emulated power well is inactive.

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