MEC1632 datasheet(68/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 68

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When matching LPC I/O addresses, the MEC1632 ignores address bits that correspond to ‘1b’ bits in the MASK field.

When forming the AHB address from the LPC I/O address, the LPC I/O address bits that correspond to the ‘1b’ bits in

the MASK are passed through to the AHB address. For example, the Keyboard Controller (8042) Base Address Register

has 60h in the LPC Address field, the Frame field is 01h, and the MASK field is 04h. Because of the single ‘1b’ bit in

MASK, the BAR will match LPC I/O patterns in the form ‘00000000011000b’, so both 60h and 64h will be matched and

claimed by the MEC1632. When forming the AHB address, the Frame number 01h will be put in bit positions 15 through

10 and concatenated with FF_0000h, to form the Keyboard Controller Frame base address of FF_0400h. If the Host

reads from address 60h, a read access will be initiated to AHB address FF_0400h (the base address OR’d with bit 2

from 60h). If the Host reads from address 64h, a read access will be initiated to AHB address FF_0404h (again, bit 2

from the LPC I/O address is OR’d into the AHB address).

As another example, if a standard 16550 UART was located at LPC I/O address 238h, then the UART Receive buffer

would appear at address 238h and the Line Status register at 23Dh. If the BAR for the UART was set to 0238_8047h,

then the UART will be matched at I/O address 238h, the UART is located in Logical Device 6h, the UART is enabled

and the UART device includes 8 registers. The Receive buffer would map to AHB address FF_1800h and the Line Sta-

tus register would map to AHB address FF_1805h.

5.6.4

BASE ADDRESS REGISTER TABLE

Table 5-6, "Base Address Registers Default Values", lists the Base Address Registers for all logical devices on the

MEC1632. The BAR EC Offsets are relative to the base address of the LPC Logical Device, which is located at AHB

address FF_3000h. The columns to the right of the heavy line show the field definitions for the default values listed in

the column labeled “Reset Default”. Shaded fields in Table 5-6 are read-only.

The EC can read and write the BAR table entries with 32-bit, 16-bit or 8-bit accesses. The Host accesses the BAR table

using 8-bit reads and writes.

The shaded LPC I/O Address, VALID, FRAME, MASK fields are read-only Table 5-6. The unshaded fields has read/write

access.

FIGURE 5-1:

LPC BAR MAPPING

Note:

The BAR at offset 360h associated with the LPC Interface is different in that LPC I/O accesses that are

claimed by this BAR does not translate directly into a AHB addresses. Addresses that are claimed by this

BAR, the Configuration Port BAR, are used to manage Configuration Registers. These accesses are

described in Section 5.5, on page 65. This BAR is also special in that a byte write to offset 362h (bits[7:0]

of the LPC Host Address field) does not directly write into the BAR. Instead, the byte is held in a buffer. A

byte write to offset 363h will both write the byte at offset 363h and will copy the buffer into offset 362h. This

is done to insure that the 16-bit LPC Host Address field of the Configuration Port BAR is always completely

updated in one cycle.

BAR.Frame

LPC Address &

BAR.Mask

~D = ~BAR.Device

11 11 1 1 1 ~D

0 0

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