MEC1632 datasheet(84/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 84

 2012-2018 Microchip Technology Inc.

6.5

Host Interrupts to EC

The LRESET# reset signal and the LPCPD# power down signal can be used to generate EC interrupts and wake-up

events. The edge detection of the interrupt and wake events are controlled by their associated Pin Control Register on

page 396. The interrupts are routed to the LRESET# and LPCPD# bits in the GIRQ14 Source Register on page 311.

The LPC Logical Device can generate an additional interrupt to the EC when a Host access is mapped to the AHB bus.

Bit LPC_AHB_ERR in the Host Bus Error Register is set when an LPC-sourced AHB bus access causes an error; it is

also routed to the LPC_AHB_ERR bit in the GIRQ14 Source Register on page 311. For details see Section 6.10.2, "Host

Bus Error Register," on page 91.

6.6

EC Interrupts to Host

The Embedded Controller can send an interrupt to the Host on any Serial Interrupt Request channel using the EC SER-

IRQ Register in conjunction with the SERIRQ Configuration Registers.

6.7

LPC Clock Run and LPC Power Down Behavior

The LPCPD# signal (see the Intel Low Pin Count Specification, Section 8.1) and the CLKRUN# signal (see the Intel Low

Pin Count Specification, Section 8.2) are implemented in the MEC1632.

6.7.1

USING LPCPD#

The MEC1632 tolerates the LPCPD# signal going active and then inactive again without LRESET# going active. This

is a requirement for notebook power management functions.

The LPC Bus Specification, Rev. 1.0, Section 8.2 states that “After LPCPD# goes back inactive, the LPC I/F will always

be reset using LRST#”. This text must be qualified for mobile systems where it is possible that when exiting a “light”

sleep state (ACPI S1, APM POS), LPCPD# may be asserted but the LPC Bus power may not be removed, in which

case LRESET# will not occur. When exiting a “deeper” sleep state (ACPI S3-S5, APM STR, STD, soft-off), LRESET#

will occur.

The LPCPD# pin is implemented as a “local” powergood for the LPC bus in the MEC1632. It is not to be used as a global

powergood for the chip. It is used to minimize the LPC power dissipation.

Prior to going to a low-power state, the system asserts the LPCPD# signal. LPCPD# goes active at least 30 microsec-

onds prior to the LCLK signal stopping low and power being shut to the other LPC interface signals. Upon recognizing

LPCPD# active, there are no further transactions on the LPC interface.

6.7.2

USING CLKRUN#

CLKRUN# is used to indicate the PCI clock status as well as to request that a stopped clock be started. See FIGURE

6-3: CLKRUN# System Implementation Example on page 85, an example of a typical system implementation using

CLKRUN#.

PCI Clock Run Support can be enabled and disabled using the Bit[2] SerIRQ Mode in the Device Mode register, Global

Configuration Register 24h (see Table 5-15, “Chip-Level (Global) Control/Configuration Registers,” on page 78). When

the Bit[2] SerIRQ Mode is ‘0,’ Serial IRQs are disabled, the CLKRUN# pin is disabled, and the affects of Interrupts on

CLKRUN# are ignored. When the Bit[2] SerIRQ Mode is ‘1,’ Serial IRQs are enabled, the CLKRUN# pin is enabled,

and the CLKRUN# support related to Interrupts as described in the section below is enabled.

The CLKRUN# pin is an open drain output and input. Refer to the PCI Mobile Design Guide Rev 1.0 for a description

of the CLKRUN# function. If CLKRUN# is sampled “high”, the PCI clock is stopped or stopping. If CLKRUN# is sampled

“low”, the PCI clock is starting or started (running). CLKRUN# in the MEC1632 supports Serial IRQ cycles.

6.7.2.1

CLKRUN# Support for Serial IRQ Cycle

If a device in the MEC1632 asserts or de-asserts an interrupt and CLKRUN# is sampled “high”, the MEC1632 can

request the restoration of the clock by asserting the CLKRUN# signal asynchronously (Table 6-3). The MEC1632 holds

CLKRUN# low until it detects two rising edges of the clock. After the second clock edge, the MEC1632 must disable the

open drain driver (Figure 6-4).

The MEC1632 must not assert CLKRUN# if it is already driven low by the central resource; i.e., the PCI CLOCK GEN-

ERATOR in Figure 6-4. The MEC1632 will not assert CLKRUN# under any conditions if the Serial IRQs are disabled.

The MEC1632 must not assert CLKRUN# unless the line has been de-asserted for two successive clocks; i.e., before

the clock was stopped (Figure 6-4).

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