MEC1632 datasheet(108/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 108

 2012-2018 Microchip Technology Inc.

7.4.9

MASTER CLOCK TREES

7.4.9.1

Description

The master clock derived from the 20 MHz Oscillator is branched into six internal clock trees in the MEC1632. These

Master Clock Trees are controlled by register bits in the Clock Tree Control 0 Register and Clock Tree Control 1 Register

and function as defined in Section 7.4.9.4, "Control Bit Encoding," on page 110 and Section 7.4.9.2, "Dynamic Clock

Tree Gating," on page 108.The Block Allocation Per Clock Tree is defined in Section 7.4.9.3.

Each master clock tree can be forced ‘on,’ forced ‘off,’ or dynamically controlled by hardware to help minimize power

consumption throughout the EC Controlled Dynamic Power States. See also Section 7.4.10.3, "Clock tree Gating in

Heavy Sleep," on page 114.

7.4.9.2

Dynamic Clock Tree Gating

7.4.9.2.1

Overview

Dynamic Clock Tree Gating specifies that a master clock tree is ‘on’ if any one of the blocks allocated to that tree requires

a clock, or if a bus master is accessing registers in that tree. Clock trees are ‘off’ when the bits in the Clock Required

Status Registers that are associated with the blocks in a tree are not asserted and a bus master is not accessing regis-

ters in the tree.

FIGURE 7-11:

Generic Block Clocking Model CLOCK GATING STATE DIAGRAM EXAMPLE

RUNNING STATE

(CLK_REQ = ‘1’)

SLEEPING STATE

(CLK_REQ = ‘0’)

PREPARING TO

SLEEP STATE

(CLK_REQ = ‘1’)

DISABLED STATE

(CLK_REQ = ‘0’)

RESET

INTERNAL_ENABLE=’1'

INTERNAL_ENABLE=‘0’

EXTERNAL_SLEEP_INPUT=’0'

INTERNAL_ENABLE=’0'

EXTERNAL_SLEEP_INPUT=’1'

EXTERNAL_SLEEP_INPUT=’0'

IDLE=’0'

IDLE=’1'

EXTERNAL_SLEEP_INPUT=’0'

EXTERNAL_SLEEP_INPUT=’1'

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