PS37044AJOFDDFR datasheet(22/34 Pages) TI

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9.2 Typical Application

9.2.1 Design 1: Multi-Rail Window Monitoring for Microcontroller Power Rails

A typical application for the TPS37042 is shown in Figure 9-3. The TPS37042 is used to monitor two PMIC

voltage rails that powers the core and I/O voltage of the microcontroller that requires accurate reset delay and

voltage supervision. It utilizes the TPS37042 to monitor the core voltage rail of a MCU similar to the circuit below.

TPS37042

SENSE1

RESET1

VDD

GND

VDD

VOUT1

PMIC

VDD

VCORE

VI/O

VOUT2

VIN

VDD

Microcontroller

RESET

10 kΩ

SENSE2

RESET2

Figure 9-3. TPS37042 Dual-Channel Monitoring Two Microcontroller Power Rails

9.2.1.1 Design Requirements

Table 9-1. Design Requirements

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

Monitored rails

3.3-VI/O nominal, with alerts if outside of ±8% of 3.3 V

(including device accuracy), 10 ms reset delay

Worst case VIT+(OV) = 3.533 V (7.06%)

Worst case VIT–(UV) = 3.071 V (-6.94%)

1.2-VCORE nominal, with alerts if outside of ±5% of 1.2 V

(including device accuracy), 10 ms reset delay

Worst case VIT+(OV) = 1.2484 V (4.03%)

Worst case VIT–(UV) = 1.1524 V (-3.97%)

Output logic voltage

5-V CMOS

Maximum system supervision

current consumption

25 µA

5.5 µA (15 µA max)

9.2.1.2 Detailed Design Procedure

Determine which version of the TPS3704x best suits the monitored rail (VMON) and window tolerances found on

Table 12-2. The TPS3704x allows overvoltage and undervoltage monitoring for precise voltage supervision of

common rails between 0.4 V and 5.55 V. This application calls for very tight monitoring of the rail with only ±5%

of variation allowed on the 1.2-VCORE rail. To ensure this requirement is met, the TPS37042 was chosen for its

±3% thresholds. The 3.3-VI/O is more flexible and can operate up to 8% variance. Since the TPS3704x comes in

various tolerance options, the ±6% thresholds can be chosen for this voltage rail. To calculate the worst-case for

VIT+(OV) and VIT-(UV), the accuracy must also be taken into account. The worst-case for VIT+(OV) and VIT-(UV) can

be calculated shown in Equation 5 and Equation 6 respectively:

VIT+(OV-Worst Case) = VMON × (1 + %Threshold ) × (1 + %Accuracy) = 1.2 × (1.03) × (1.01) = 1.2484 V

(5)

VIT-(UV-Worst Case) = VMON × (1 - %Threshold) × (1 - %Accuracy) = 1.2 × (0.97) × (0.99) = 1.1524V

(6)

Hysteresis is also needed to be taken into account when determining the OV and UV thresholds such that the

release point after the fault is higher than the power supply tolerance limits. Refer to Figure 7-1 for more details.

When the outputs switch to a high impedance state, the rise time of the RESETx/RESETx pin depends on the

pull-up resistance and the capacitance on that node. Choose pull-up resistors that satisfy both the downstream

timing requirements and the sink current required to have a VOL low enough for the application; 10 kΩ to 1 MΩ

resistors are a good choice for low-capacitive loads.

TPS3704

SNVSBZ2B – MARCH 2021 – REVISED DECEMBER 2021

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