PS37044AJOFDDFR datasheet(8/34 Pages) TI

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7.6 Timing Requirements

At 1.7 V ≤ VDD ≤ 6.0 V, RESETx voltage (VRESETx) = 10 kΩ to VDD, RESETx load = 10 pF, and over the operating free-air

temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C, typical conditions at VDD =

3.3 V.

PARAMETER

TEST CONDITIONS

MIN NOM MAX UNIT

Reset release time delay

Fixed delay option tD < 4 ms, overdrive = 10%

-40

Reset release time delay

Fixed delay option tD > 5 ms, overdrive = 10%

-30

tPD

Propagation detect delay (1)

Fixed time delay tD > 1 ms, overdrive 10%

µs

tGI(VIT-) Glitch Immunity Undervoltage (5% overdrive) (2)

µs

tGI(VIT+) Glitch Immunity Overvoltage (5% overdrive) (2)

µs

Ouptut rise (Push-Pull) (2) (3)

Output rise time (Open-Drain) (2) (3)

2.2

µs

Output fall time (2) (3)

0.2

µs

tSTRT

Startup delay (4)

(1)

tPD measured from threshold trip point (VIT-(UV) or VIT+(OV)) to RESETx VOL voltage

(2)

5% Overdrive from threshold. Overdrive % = [(VSENSEx - VIT) / VIT]; Where VIT stands for VIT-(UV) or VIT+(OV)

(3)

Output transitions from VOL to VOH or (VRESETx) for rise times and VOH or (VRESETx) to VOL for fall times.

(4)

During the power-on sequence, VDD must be at or above VDD(MIN) for at least tSTRT + tD before the output is in the correct state. when

VDD is between VDD(MIN) and VPOR the RESETx pin will be engaged

TPS3704

SNVSBZ2B – MARCH 2021 – REVISED DECEMBER 2021

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