VDD

BANDGAP

+

–

+

–

VBG

UNDERVOLTAGE

OVERVOLTAGE

SENSE1

POR

OTP

OSCILLATOR

CLK

CLK

TIME DELAY

(counter)

UVLO

+

–

VDD

UVLO

VBG

SENSE1

GND

VBG

SENSE1

SENSE3

+

–

+

–

UNDERVOLTAGE

OVERVOLTAGE

SENSE2

CLK

TIME DELAY

(counter)

UVLO

RESET1

VBG

SENSE2

RESET2

SENSE2

SENSE4

(SENSE1 and SENSE2)

(SENSE3 and SENSE4)

Figure 8-4. TPS37044 Quadruple-Channel Functional Block Diagram

*For available voltages, window tolerance, time delays, and UV/OV threshold options, see Table 12-2.

8.3 Feature Description

8.3.1 VDD

The TPS3704x is designed to operate from an input voltage supply range between 1.7 V to 6 V. The SENSEx

pins is monitored by the internal comparator. VDD also functions as the supply for the internal bandgap, internal

regulator, state machine, buffers and other control blocks. The reset signal is at a known state when VDD >

voltage.

VDD capacitor is not required for this device; however, if the input supply is noisy, then it is good design practice

to place a 0.1 μF to 1 µF bypass capacitor between the VDD pin and the GND pin to ensure enough charge is

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TPS3704

SNVSBZ2B – MARCH 2021 – REVISED DECEMBER 2021

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