PS37044AJOFDDFR datasheet(19/34 Pages) TI

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8.3.3 RESETx/RESETx

In a typical TPS3704x application, the RESETx/RESETx output is connected to a reset or enable input of

a processor [such as a digital signal processor (DSP), application-specific integrated circuit (ASIC), or other

processor type] or the enable input of a voltage regulator [such as a DC-DC converter or low-dropout regulator

(LDO)].

The TPS3704x has open drain active low outputs that requires an external pull-up resistor to hold these lines

high to the required voltage logic. Connect the external pull-up resistor to the proper voltage rail to enable the

output to be connected to other devices at the correct interface voltage levels. To ensure proper voltage levels,

give some consideration when choosing the external pull-up resistor values. The external pull-up resistor value is

determined by VOL, output capacitive loading, and output leakage current. These values are specified in

Section 7.5. The open drain output can be connected as a wired-OR logic with the other RESETx/RESETx open

drain pins.

tPD

VSENSEx

UV Limit

VIT+(OV)

VIT+(OV) - VHYS

VIT-(UV)

VIT-(UV) + VHYS

RESETx

OV Limit

tPD

Figure 8-6. RESETx output

8.4 Device Functional Modes

Table 8-1. Functional Mode Truth Table

DESCRIPTION

CONDITION

VDD PIN

OUTPUT RESETx /

(RESETx) PIN

Normal Operation

VIT–(UV) < SENSEx < VIT+(OV)

VDD > VDD(MIN)

High / (Low)

Normal Operation (UV Only)

SENSEx > VIT-(UV)

VDD > VDD(MIN)

High / (Low)

Over Voltage detection

SENSEx > VIT+(OV)

VDD > VDD(MIN)

Low / (High)

Under Voltage detection

SENSEx < VIT-(UV)

VDD > VDD(MIN)

Low / (High)

UVLO engaged

VIT–(UV) < SENSEx < VIT+(OV)

VPOR < VDD < UVLO

Low / (High)

8.4.1 Normal Operation (VDD > VDD(MIN))

When the voltage on VDD is greater than VDD(MIN) for approximately (tSTRT + tD), the RESETx/RESETx output

state will correspond to the SENSEx pin voltage with respect to the threshold limits, when SENSEx voltage is

outside of threshold limits the RESETx/RESETx voltage will be asserted.

8.4.2 Undervoltage Lockout (VPOR < VDD < UVLO)

When the voltage on VDD is less than the device UVLO voltage but greater than the power-on reset voltage

(VPOR), the RESETx/RESETx pin will be asserted, regardless of the voltage on SENSEx pin.

8.4.3 Power-On Reset (VDD < VPOR)

When the voltage on VDD is lower than the required voltage (VPOR) to internally pull the asserted output to GND,

RESETx/RESETx signal is undefined and is not to be relied upon for proper device function.

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TPS3704

SNVSBZ2B – MARCH 2021 – REVISED DECEMBER 2021

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