Z8F082ASH020SC datasheet(181/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

Oscillator Control

Z8 Encore! XP® F08xA Series

Product Specification

163

the Watch-Dog Timer failure can be detected. A very slow system clock results in very

slow detection times.

It is possible to disable the clock failure detection circuitry as well as all functioning

clock sources. In this case, the Z8 Encore! XP® F08xA Series device ceases functioning

and can only be recovered by Power-On-Reset.

Oscillator Control Register Definitions

Oscillator Control Register

The Oscillator Control Register (OSCCTL) enables/disables the various oscillator circuits,

enables/disables the failure detection/recovery circuitry and selects the primary oscillator,

which becomes the system clock.

The Oscillator Control Register must be unlocked before writing. Writing the two step

sequence E7H followed by 18H to the Oscillator Control Register unlocks it. The register

is locked at successful completion of a register write to the OSCCTL.

INTEN—Internal Precision Oscillator Enable

1 = Internal precision oscillator is enabled

0 = Internal precision oscillator is disabled

XTLEN—Crystal Oscillator Enable; this setting overrides the GPIO register control for

PA0 and PA1

1 = Crystal oscillator is enabled

0 = Crystal oscillator is disabled

WDTEN—Watchdog Timer Oscillator Enable

1 = Watch-Dog Timer oscillator is enabled

0 = Watch-Dog Timer oscillator is disabled

POFEN—Primary Oscillator Failure Detection Enable

1 = Failure detection and recovery of primary oscillator is enabled

0 = Failure detection and recovery of primary oscillator is disabled

Table 102. Oscillator Control Register (OSCCTL)

BITS

FIELD

INTEN

XTLEN

WDTEN

POFEN

WDFEN

SCKSEL

RESET

010

R/W

R/WR/W

ADDR

F86H

Caution:

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