Z8F082ASH020SC datasheet(44/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

Reset and STOP Mode Recovery

Z8 Encore! XP® F08xA Series

Product Specification

STOP Mode Recovery Using the External RESET Pin

When the Z8 Encore! XP® F08xA Series device is in STOP Mode and the external

RESET pin is driven Low, a system reset occurs. Because of a glitch filter operating on the

RESET pin, the Low pulse must be greater than the minimum width specified, or it is

ignored. See “Electrical Characteristics” on page 191 for details.

Reset Register Definitions

Reset Status Register

The Reset Status (RSTSTAT) register is a read-only register that indicates the source of

the most recent Reset event, indicates a STOP Mode Recovery event, and indicates a

Watch-Dog Timer time-out. Reading this register resets the upper four bits to 0.

This register shares its address with the Watch-Dog Timer control register, which is write-

only (Table 11).

POR—Power-On Reset Indicator

If this bit is set to 1, a Power-On Reset event occurred. This bit is reset to 0 if a WDT time-

out or STOP Mode Recovery occurs. This bit is also reset to 0 when the register is read.

STOP—STOP Mode Recovery Indicator

If this bit is set to 1, a STOP Mode Recovery occurred. If the STOP and WDT bits are both

Table 11. Reset Status Register (RSTSTAT)

BITS

FIELD

POR

STOP

WDT

EXT

Reserved

RESET

See descriptions below

R/W

RRR

ADDR

FF0H

Reset or STOP Mode Recovery Event

POR

STOP

WDT

EXT

Power-On Reset

1000

Reset using RESET pin assertion

0001

Reset using Watch-Dog Timer time-out

0010

Reset using the On-Chip Debugger (OCTCTL[1] set to 1)

1000

Reset from STOP Mode using DBG Pin driven Low

1000

STOP Mode Recovery using GPIO pin transition

0100

STOP Mode Recovery using Watch-Dog Timer time-out

0110

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