Z8F082ASH020SC datasheet(73/244 Pages) ZILOG

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PS024705-0405

P R E L I M I N A R Y

Interrupt Controller

Z8 Encore! XP® F08xA Series

Product Specification

PA6CENH—Port A Bit[6] or Comparator Interrupt Request Enable Low Bit

PAxENL—Port A Bit[x] Interrupt Request Enable Low Bit

IRQ2 Enable High and Low Bit Registers

Table 41 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg-

isters (Tables 42 and 43) form a priority encoded enabling for interrupts in the Interrupt

Request 2 register. Priority is generated by setting bits in each register.

Reserved—Must be 0.

C3ENH—Port C3 Interrupt Request Enable High Bit

C2ENH—Port C2 Interrupt Request Enable High Bit

Table 40. IRQ1 Enable Low Bit Register (IRQ1ENL)

BITS

FIELD

PA7ENL

PA6CENL

PA5ENL

PA4ENL

PA3ENL

PA2ENL

PA1ENL

PA0ENL

RESET

000

R/W

R/WR/W

ADDR

FC5H

Table 41. IRQ2 Enable and Priority Encoding

IRQ2ENH[x]IRQ2ENL[x] Priority

Description

Disabled

Level 1

Low

Level 2

Nominal

Level 3

High

where x indicates the register bits from 0–7.

Table 42. IRQ2 Enable High Bit Register (IRQ2ENH)

BITS

FIELD

Reserved

C3ENH

C2ENH

C1ENH

C0ENH

RESET

000

R/W

R/WR/W

ADDR

FC7H

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