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Z8F082ASH020SC bảng dữ liệu(PDF) 135 Page - Zilog, Inc. |
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Z8F082ASH020SC bảng dữ liệu(HTML) 135 Page - Zilog, Inc. |
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135 / 244 page ![]() PS024705-0405 P R E L I M I N A R Y Analog-to-Digital Converter Z8 Encore! XP® F08xA Series Product Specification 117 ADC Control Register Definitions ADC Control Register 0 The ADC Control register selects the analog input channel and initiates the analog-to-dig- ital conversion. CEN—Conversion Enable 0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically clears this bit to 0 when a conversion is complete. 1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is already in progress, the conversion restarts. This bit remains 1 until the conversion is complete. REFSELL—Voltage Reference Level Select Low Bit; in conjunction with the High bit (REFSELH) in ADC Control/Status Register 1, this determines the level of the internal volt- age reference; the following details the effects of {REFSELH, REFSELL}; note that this reference is independent of the Comparator reference 00= Internal Reference Disabled, reference comes from external pin 01= Internal Reference set to 1.0 V 10= Internal Reference set to 2.0 V (default) 11= Reserved REFEXT - External Reference Select 0 = External reference buffer is disabled; Vref pin is available for GPIO functions 1 = The internal ADC reference is buffered and connected to the Vref pin CONT 0 = Single-shot conversion. ADC data is output once at completion of the 5129 system clock cycles 1 = Continuous conversion. ADC data updated every 256 system clock cycles ANAIN[3:0]—Analog Input Select These bits select the analog input for conversion. Not all Port pins in this list are available in all packages for the Z8 Encore! XP® F08xA Series. Refer to the chapter “Pin Descrip- tion” on page 7 for information regarding the Port pins available with each package style. Do not enable unavailable analog inputs. Usage of these bits changes depending on the buffer mode selected in ADC Control/Status Register 1. Table 70. ADC Control Register 0 (ADCCTL0) BITS 7 6 5 4 3 2 1 0 FIELD CEN REFSELL REFEXT CONT ANAIN[3:0] RESET 0 000 00 00 R/W R/WR/W R/WR/W R/WR/W R/WR/W ADDR F70H |
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