P5021 datasheet(107/155 Pages) NXP

107 / 155 page

Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

107

Figure 41. Single-ended measurement points for rise and fall time matching

2.20.2.4

Spread-spectrum clock

SD_REF_CLK1/SD_REF_CLK1 were designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30–33 kHz rate

is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended

modulation should be used.

SD_REF_CLK2/SD_REF_CLK2 were designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30–33 kHz rate

is allowed), assuming both ends have same reference clock and the industry protocol specifications supports it. For better

results, a source without significant unintended modulation should be used.

SD_REF_CLK3/SD_REF_CLK3 are not intended to be used with, and should not be clocked by, a spread spectrum clock

source.

SD_REF_CLK4/SD_REF_CLK4 are not intended to be used with, and should not be clocked by, a spread spectrum clock

source.

2.20.3

SerDes transmitter and receiver reference circuits

This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.

Figure 42. SerDes transmitter and receiver reference circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below based on the application

usage:

•

Section 2.20.4, “PCI Express”

•

Section 2.20.5, “XAUI”

•

Section 2.20.6, “Aurora”

•

Section 2.20.7, “Serial ATA (SATA)

•

Section 2.20.8, “SGMII interface”

Note that external AC-coupling capacitor is required for the above serial transmission protocols per the protocol’s standard

requirements.

SDn_REF_CLK

VCROSS MEDIAN

VCROSS MEDIAN + 100 mV

VCROSS MEDIAN – 100 mV

TFALL

TRISE

Receiver

Transmitter

SD_TXn

SD_RXn

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