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ATXP032

DS-ATXP032–114I–4-2020

The WEL bit in the Status/Control Register is reset back to the logic “0” state if the erase cycle aborts due to an

incomplete address being sent, the CS pin being deasserted before a whole byte is finished, or because a memory

location within the region to be erased is protected.

While the device is executing a successful erase cycle, the Status/Control register can be read and indicates that

the device is busy. For faster throughput, it is recommended that the Status/Control register be polled rather than

waiting for the t

BLKE time to determine if the device has finished erasing. At some point before the erase cycle

completes, the WEL bit in the Status/Control register is reset back to the logic “0” state.

For fastest throughput and least power consumption, it is recommended that the Active Status Interrupt command

25h be used. After the initial 16 clocks, no more clocks are required. Once the BUSY cycle is done, SO is driven

low immediately to signal the device has finished erasing.

The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase

properly. If an erase error occurs, it is indicated by the EPE bit in the Status/Control Register.

Figure 9-13. Block Erase

Figure 9-14. Block Erase in Octal Mode —SDR

SCK

10 11

37 38

35 36

Opcode (20h, 52h or D8h)

Address Bits A31-A0

High-Impedance

MSB

A23-16

A15-8

A7-0

A31-24

Address

Opcode

(20h, 52h

or D8h)

I/O7-0

SCK

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