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ATXP032 bảng dữ liệu(PDF) 67 Page - Dialog Semiconductor |
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ATXP032 bảng dữ liệu(HTML) 67 Page - Dialog Semiconductor |
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67 / 113 page  65 ATXP032 DS-ATXP032–114I–4-2020 After the address byte and the dummy cycles have been clocked in, additional clock cycles result in data being output on the I/O pin(s). The data is always output with the MSB of a byte first. If Status/Control Register Byte 1 is read first, it is directly followed by Status/Control register byte 2 and so on. The output values for addresses higher than 3 are not defined in this device. Note that for octal DDR mode, Status/Control register bytes are output on both edges of the SCK pulse. When reading just a single register (on the rising SCK edge), the next register location is also read out (on the falling SCK edge). When reading all three registers, the following register location is also read out (on the falling edge of the 2nd SCK clock). If the extra register location read out is not with address 1 - 3, the value read out is undefined. Deasserting the CS pin terminates the read operation and put the I/O pin(s) used into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 12-1. Read Status/Control Registers Figure 12-2. Read Status/Control Registers in Octal Mode — SDR D D D D D D D D X X X X X X X X A A A A A A A A MSB MSB LSB MSB 0 1 1 0 0 1 0 1 Output Data Byte 1 1 Dummy Byte Address Bits A7-A0 Opcode DS 2 3 1 0 6 7 5 4 10 11 9 8 12 13 16 17 15 14 20 18 22 23 26 27 25 24 21 28 30 29 19 SI SCK SO CS Byte1 Byte2 Output Data 4 Dummy Cycles A7-0 Address 65h Opcode 2 3 1 0 4 6 5 I/O7-0 SCK CS DS |
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