ATXP032 datasheet(64/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

The number of dummy clocks in Table 12-8 below refers to full clock cycles on the SCK pin, both for SDR and DDR

modes.

Refer to section Section 8.1, Read Array (0Bh and 03h) and Section 8.2, Burst Read with Wrap (0Ch) for additional

details.

Table 12-6. Status/Control Register Byte 3

Bit

Acronym

Name

Type

Default

Description

Wrap Length

R/W

Used to set wrap length. See

Table 12-7, Wrap Bit

Functions — W[7:5].

Default value is 000.

R/W

WPP

Write Protect (WP)

Pin Status

WP is asserted.

WP is deasserted.

Dummy Clocks

R/W

Used to set number of dummy clock cycles.

See

Table 12-8, Dummy Clock Cycles and

Maximum Operating Frequency — -40

oC to +85

oC.

Default value is 0x7.

R/W

Table 12-7. Wrap Bit Functions — W[7:5]

Wrap Length

Wrap Around

8-byte

Continuous on same 8-byte line (Default)

16-byte

Continuous on same 16-byte line

32-byte

Continuous on same 32-byte line

N/A

N/A, do not use this wrap bit combination

8-byte

Once, then continue at the beginning of the next 8-byte line

16-byte

Once, then continue at the beginning of the next 16-byte line

32-byte

Once, then continue at the beginning of the next 32-byte line

N/A

N/A, do not use this wrap bit combination

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