ATXP032 datasheet(47/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

31 - A0 is set to the logic “1” state and the sector itself is then protected from program and erase operations. In

addition, the WEL bit in the Status/Control register is reset back to the logic “0” state.

The complete four address bytes must be clocked into the device before the CS pin is deasserted, and the CS pin

must be deasserted on a whole byte boundary (multiples of eight bits); otherwise, the device aborts the operation,

the state of the Sector Protection Register is unchanged, and the WEL bit in the Status/Control register is reset to

a logic “0”.

As a safeguard against accidental or erroneous sector protection or lack of protection, the Sector Protection

Registers can themselves be locked from updates by using the SPRL (Sector Protection Registers Locked) bit of

the Status/Control register. For more information, refer to Section 12.1, Status/Control Register Byte 1. If the

Sector Protection registers are locked, then any attempts to issue the Protect Sector command are ignored, and

the device resets the WEL bit in the Status/Control register back to a logic “0” and return to the idle state once the

CS pin has been deasserted.

Figure 10-7. Protect Sector

Figure 10-8. Protect Sector in Octal Mode — SDR

SCK

MSB

10 11

37 38

35 36

Opcode

Address Bits A31-A0

High-Impedance

A23-16

A15-8

A7-0

A31-24

Address

36h

Opcode

I/O7-0

SCK

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