ATXP032 datasheet(70/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

It is not possible to write both the volatile and the non-volatile registers at the same time. Non-volatile registers are

only written if the command specifies the address of a non-volatile register.

Writing to other addresses than the ones listed in Table 12-1 or Table 12-2 is not supported.

There is no wrap around on the address field. When writing multiple volatile Status/Control registers in a single

operation, the registers have to be clocked in ascending order.

When writing to registers, bits that are read only or reserved for future use should be written as 0.

Before the Write Status Registers command can be issued, the Write Enable command must have been previously

issued to set the WEL bit in the Status/Control register to a logic “1”.

To issue the Write Status Registers command, the CS pin must first be asserted and the 71h command must be

clocked into the device. After the command has been clocked in, one address byte must be clocked in to specify at

which register to start the write operation, followed by one or more bytes of data. See Table 12-1 to Table 12-6 for

details about register values.

When the CS pin is deasserted, the rewritable bits in the registers are modified, and the WEL bit in the

Status/Control register is reset back to a logic “0”.

The address byte and at least one complete byte of data must be clocked into the device before the CS pin is

deasserted, and the CS pin must be deasserted on whole byte boundaries (multiples of eight bits); otherwise, the

device aborts the operation and no data is programmed into the registers, and the WEL bit in the Status/Control

When writing volatile Status/Control registers in octal DDR mode, the address given has to be for the single

have to be issued.

When writing non-volatile Status/Control registers in Octal DDR mode, the address given can be odd or even, and

a single register is written.

If the WP pin is asserted, then the SPRL bit can only be set to a logic “1”. If an attempt is made to reset the SPRL

bit to a logic “0” while the WP pin is asserted, then the Write Status Registers command will be ignored, and the

WEL bit in the Status/Control register is reset back to the logic “0” state. In order to reset the SPRL bit to a logic “0”,

the WP pin must be deasserted.

Note: No other commands should be issued while this operation is in progress. As changes to the Status/Control

registers will change the configuration of I/O pins, users should wait tWRSR (for volatile registers) or tWRSRNV (for non-

volatile registers) before issuing further commands.

Figure 12-7. Write Status Registers

SCK

MSB

10 11

13 14

18 19

16 17

Opcode

High-Impedance

A A A A

A A A

MSB

D D D D D D D D

Address Bits A7-A0

Data In Byte 1

MSB

Data In Byte n

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