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ATXP032

DS-ATXP032–114I–4-2020

12.9

Write Status Register Byte 2 (31h)

The Write Status Register Byte 2 command is used to modify the Status/Control register byte 2 bits. Using the

Write Status Register Byte 2 command is the only way to modify the TERE and SDR/DDR bits in Status/Control

the Enter Octal Mode (E8h) and Return to Standard SPI Mode (FFh) commands.

Before the Write Status Register Byte 2 command can be issued, the Write Enable command must have been

previously issued to set the WEL bit in the Status/Control register to a logic 1.

To issue the Write Status Register Byte 2 command, the CS pin must first be asserted and then the command 31h

must be clocked into the device followed by one byte of data. The one byte of data consists of the bits described in

Table 12-5. Any additional data bytes sent to the device are ignored. When the CS pin is deasserted, the TERE bit

in the Status/Control register is modified, and the WEL bit in the Status/Control register is reset back to a logic 0.

The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin

must be deasserted on whole byte boundaries (multiples of eight bits); otherwise, the device aborts the operation,

the state of the TERE bit does not change, and the WEL bit in the Status/Control register is reset back to the logic

0 state.

Figure 12-13. Write Status Register Byte 2

Figure 12-14. Write Status Register Byte 2 in Octal Mode — SDR

SCK

MSB

10 11

13 14

Opcode

High-Impedance

MSB

D D D D D D D D

Status Register 2

Byte

Data

31h

Opcode

I/O7-0

SCK

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