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ATXP032 bảng dữ liệu(PDF) 30 Page - Dialog Semiconductor

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ATXP032
DS-ATXP032–114I–4-2020
time to determine if the data bytes have finished programming. For fastest throughput and least power
consumption, it is recommended that the Active Status Interrupt command 25h be used. After the initial 16 clocks,
no more clocks are required. Once the BUSY cycle is done, SO will be driven low immediately to signal the device
has finished programming. At some point before the program cycle completes, the WEL bit in the Status/Control
register is reset back to the logic “0” state.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to
program properly. If a programming error arises, it is indicated by the EPE bit in the Status/Control register.
Note that in octal DDR mode, the byte program operation programs two bytes instead of one, and the page
program operation programs an even number of bytes. Address bit A
0 has to be 0 in this case.
Figure 9-1.
Byte Program
Figure 9-2.
Byte Program in Octal Mode — SDR
SCK
CS
SI
SO
MSB
MSB
2
3
1
0
0
0
0
0
0
0
1
0
6
7
5
4
10 11
9
8
12
39
37 38
44
47
46
45
42 43
40 41
Opcode
High-Impedance
A A A A
A A A
A A
MSB
D D D D D D D D
Address Bits A31-A0
Data In
DS
Byte
Data In
A23-16
A15-8
A7-0
A31-24
Address
02h
Opcode
1
0
5
3
4
2
I/O7-0
SCK
CS
DS



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