VR4102 datasheet(108/701 Pages) NEC

108 / 701 page

CHAPTER 4 VR4102 PIPELINE

108

(6) Store Word instruction (SW rt, offset (base))

IF stage

Same as the IF stage for the ADD instruction.

RF stage

Same as the RF stage for the LW instruction.

EX stage

Refer to the LW instruction for a calculation of the effective address. From the RF output latch,

the GPR[rt] is sent through the bypass multiplexer and into the main shifter, where the shifter

performs the byte-alignment operation for the operand. The results of the ALU are latched in the

output latches during

)1. The shift operations are latched in the output latches during )2.

DC stage

Refer to the LW instruction for a description of the cache access.

WB stage

If there was a cache hit, the content of the store data output latch is written into the data cache at

the appropriate word location.

Note that all store instructions use the data cache for two consecutive PCycles. If the following

instruction requires use of the data cache, the pipeline is slipped for one PCycle to complete the

writing of an aligned store data.

Figure 4-10. SW Instruction Pipeline Activities

IF1

Cycle

Phase

PCycle

PClock

IF2

RF1

RF2

EX1

EX2

DC1

DC2

WB1

WB2

ITLB

IDC

ITC

ICA

IDEC

DCW

DTD

DVA

DTLB

DTC

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