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VR4102 bảng dữ liệu(PDF) 218 Page - NEC

tên linh kiện VR4102
Giải thích chi tiết về linh kiện  64/32-bit Microprocessor
PDF  701 Pages
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nhà sản xuất  NEC [NEC]
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VR4102 bảng dữ liệu(HTML) 218 Page - NEC

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CHAPTER 8 CACHE MEMORY
218
8.4 CACHE STATES
(1) Cache line
The three terms below are used to describe the state of a cache line:
— Dirty: a cache line containing data that has changed since it was loaded from memory.
— Clean: a cache line that contains data that has not changed since it was loaded from memory.
— Invalid: a cache line that does not contain valid information must be marked invalid, and cannot be used. For
example, after a Soft Reset, software sets all cache lines to invalid. A cache line in any other state than
invalid is assumed to contain valid information. Neither Cold reset nor Soft reset sets caches invalid.
Software can invalidate caches.
(2) Data cache
The data cache supports three cache states:
— invalid
— valid clean
— valid dirty
(3) Instruction cache
The instruction cache supports two cache states:
— invalid
— valid
The state of a valid cache line may be modified when the processor executes a CACHE operation. CACHE
operations are described in Chapter 27.



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