VR4102 datasheet(178/701 Pages) NEC

178 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

178

6.4.5 Soft Reset Exception

Cause

A Soft Reset (sometimes called Warm Reset) occurs when the ColdReset# signal remains deasserted while the

Reset# signal goes from assertion to deassertion (for details, see Chapter 7).

A Soft Reset immediately resets all state machines, and sets the SR bit of the Status register. Execution begins

at the reset vector when the reset is deasserted. This exception is not maskable.

Caution In the VR4102, a soft reset never occurs.

Processing

The CPU provides a special interrupt vector for this exception (same location as Cold Reset):

4 0xBFC0 0000 (virtual) in 32-bit mode

4 0xFFFF FFFF BFC0 0000 (virtual) in 64-bit mode

This vector is located within unmapped and uncached address space, so that the cache and TLB need not be

initialized to process this exception. The SR bit of the Status register is set to 1 to distinguish this exception from

a Cold Reset exception.

When this exception occurs, the contents of all registers are preserved except for the following registers:

4 When ERL bit of the Status register is 0, the program counter’s value at the exception occurrence is saved

to the EPC register.

4 TS bit of the Status register is cleared to 0.

4 ERL, SR, and BEV bits of the Status register are set to 1.

During a soft reset, access to the operating cache or system interface is aborted. This means that the contents of

the cache and memory will be undefined if a Soft Reset occurs.

Servicing

The Soft Reset exception is serviced by:

4 Preserving the current processor states for diagnostic tests

4 Reinitializing the system in the same way as for a Cold Reset exception

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