PCI1520PDVG4 datasheet(83/140 Pages) TI

83 / 140 page

4−22

4.32 Card Control Register

The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register, and the

enable bit is shared between functions 0 and 1. See Table 4−11 for a complete description of the register contents.

Bit

Name

Card control

Type

Default

Card control

Offset:

91h

Type:

Read-only, Read/Write, Read/Clear

Default:

00h

Table 4−11. Card Control Register Description

BIT

SIGNAL

TYPE

FUNCTION

7†

RIENB

Ring indicate output enable.

0 = Disables any routing of RI_OUT signal (default)

1 = Enables RI_OUT signal for routing to the RI_OUT/PME terminal, when RIMUX is set to 0,

and for routing to MFUNC2 or MFUNC4

ZVENABLE

Compatibility ZV mode enable. When set, the corresponding PC Card socket interface ZV terminals enter

a high-impedance state. This bit defaults to 0.

PORT_SEL

Port select. This bit controls the priority for the ZVSEL0 and ZVSEL1 signaling if bit 6 (ZVENABLE) is set

in both functions.

0 = Socket 0 takes priority, as signaled through ZVSEL0, when both sockets are in ZV mode.

1 = Socket 1 takes priority, as signaled through ZVSEL1, when both sockets are in ZV mode.

4−3

RSVD

Reserved. Bits 4 and 3 return 0 when read.

AUD2MUX

CardBus audio-to-IRQMUX. When set, the CAUDIO CardBus signal is routed to the corresponding

multifunction terminal which may be configured for CAUDPWM. When both socket 0 and 1 functions have

AUD2MUX set, socket 0 takes precedence.

SPKROUTEN

Speaker out enable. When bit 1 is set, SPKR on the PC Card is enabled and is routed to SPKROUT. The

SPKR signal from socket 0 is XORed with the SPKR signal from socket 1 and sent to SPKROUT. The

SPKROUT terminal drives data only when the SPKROUTEN bit of either function is set. This bit is encoded

as:

0 = SPKR to SPKROUT not enabled

1 = SPKR to SPKROUT enabled

IFG

Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. Bit 0 is set when a

functional interrupt is signaled from a PC Card interface and is socket dependent (that is, not global). Write

back a 1 to clear this bit.

0 = No PC Card functional interrupt detected (default).

1 = PC Card functional interrupt detected.

† This bit is global and is accessed only through function 0.

PCI1520PDVG4 bảng dữ liệu(PDF) 83 Page - Texas Instruments

PCI1520PDVG4 bảng dữ liệu(HTML) 83 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL