PCI1520PDVG4 datasheet(64/140 Pages) TI

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4−3

4.4

Command Register

The command register provides control over the PCI1520 interface to the PCI bus. All bit functions adhere to the

definitions in PCI Local Bus Specification. None of the bit functions in this register is shared between the two PCI1520

PCI functions. Two command registers exist in the PCI1520, one for each function. Software must manipulate the

two PCI1520 functions as separate entities when enabling functionality through the command register. The

SERR_EN and PERR_EN enable bits in this register are internally wired-OR between the two functions, and these

control bits appear separately according to their software function. See Table 4−3 for a complete description of the

Bit

Name

Command

Type

Default

Command

Offset:

04h

Type:

Read-only, Read/Write

Default:

0000h

Table 4−3. Command Register Description

BIT

SIGNAL

TYPE

FUNCTION

15−10

RSVD

Reserved. Bits 15−10 return 0s when read.

FBB_EN

Fast back-to-back enable. The PCI1520 does not generate fast back-to-back transactions; therefore, bit 9

returns 0 when read.

SERR_EN

System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can

be asserted after detecting an address parity error on the PCI bus. Both bits 8 and 6 must be set for the

PCI1520 to report address parity errors.

0 = Disable SERR output driver (default)

1 = Enable SERR output driver

STEP_EN

Address/data stepping control. The PCI1520 does not support address/data stepping; therefore, bit 7 is

hardwired to 0.

PERR_EN

Parity error response enable. Bit 6 controls the PCI1520 response to parity errors through PERR. Data parity

errors are indicated by asserting PERR, whereas address parity errors are indicated by asserting SERR.

0 = PCI1520 ignores detected parity error (default)

1 = PCI1520 responds to detected parity errors

VGA_EN

VGA palette snoop. Bit 5 controls how PCI devices handle accesses to video graphics array (VGA) palette

registers.

MWI_EN

Memory write-and-invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory

write-and-Invalidate commands. The PCI1520 controller does not support memory write-and-invalidate

commands, but uses memory write commands instead; therefore, this bit is hardwired to 0.

SPECIAL

Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The PCI1520 does

not respond to special cycle operations; therefore, this bit is hardwired to 0.

MAST_EN

Bus master control. Bit 2 controls whether or not the PCI1520 can act as a PCI bus initiator (master). The

PCI1520 can take control of the PCI bus only when this bit is set.

0 = Disables the PCI1520 from generating PCI bus accesses (default)

1 = Enables the PCI1520 to generate PCI bus accesses

MEM_EN

Memory space enable. Bit 1 controls whether or not the PCI1520 can claim cycles in PCI memory space.

0 = Disables the PCI1520 from responding to memory space accesses (default)

1 = Enables the PCI1520 to respond to memory space accesses

IO_EN

I/O space control. Bit 0 controls whether or not the PCI1520 can claim cycles in PCI I/O space.

0 = Disables the PCI1520 from responding to I/O space accesses (default)

1 = Enables the PCI1520 to respond to I/O space accesses

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