T25S16AFEPR datasheet(27/74 Pages) HMSEMI

27 / 74 page

Table 6.5 Latency Cycles Versus Frequency for -40°C to 85°C/105°C at 2.3V to 3.6V

Latency Control

Read Command Maximum Frequency (MHz)

Fast Read

Dual

Output

Dual I/O

Quad

Output

Quad I/O

Word Read

Quad I/O

(legacy read latency)

104

(8 dummy)

104

(8 dummy)

104

(4 mode, 0

dummy)

104

(8 dummy)

104

(2 mode, 4

dummy)

104

(2 mode, 2

dummy)

01(2 dummy)

104

10(4 dummy)

104

11(6 dummy)

104

Notes:

1. The default dummy referred in this document is the dummy configuration when LC[1:0]=0.

2.Value guaranteed by design and/or characterization, not 100% tested in production.

6.3. Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and other

adverse system conditions that may compromise data integrity. To address this concern the ZB25VQ128

provides the following data protection mechanisms:

6.3.1 Write Protect Features



Device resets when VCC is below threshold



Time delay write disable after Power-Up



Write enable / disable commands and automatic write disable after erase or program



Command length protection

- All commands that Write, Program or Erase must complete on a byte boundary (CS# driven high after

a full 8 bits have been clocked) otherwise the command will be ignored.



Software and Hardware write protection using Status Register control

- WP# input protection

- Lock Down write protection until next power-up or Software Reset

- One-Time Program (OTP) write protection



Additional Individual Block/Sector Locks for array protection



Write Protection using the Deep Power-Down command

Upon power-up or at power-down, the

HM25Q128A

will maintain a reset condition while VCC is below the

threshold value of VWI, (see Figure 8.1). While reset, all operations are disabled and no commands are

recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related

commands are further disabled for a time delay of tPUW. This includes the Write Enable, Page Program,

Sector Erase, Block Erase, Chip Erase and the Write Status Registers commands. Note that the chip select

pin (CS#) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached.

If needed a pull-up resistor on CS# can be used to accomplish this.

After power-up the device is automatically placed in a write-disabled state with the Status Register Write

Enable Latch (WEL) set to a 0. A Write Enable command must be issued before a Page Program, Sector

Erase, Block Erase, Chip Erase or Write Status Registers command will be accepted. After completing a

program, erase or write command the Write Enable Latch (WEL) is automatically cleared to a write-disabled

state of 0.

Software controlled main flash array write protection is facilitated using the Write Status Registers

command to write the Status Register (SR1,SR2) and Block Protect (SEC, TB, BP2, BP1 and BP0) bits.

HM25Q128A

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