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T25S16AFEPR bảng dữ liệu(PDF) 48 Page - Shenzhen Huazhimei Semiconductor Co., Ltd |
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T25S16AFEPR bảng dữ liệu(HTML) 48 Page - Shenzhen Huazhimei Semiconductor Co., Ltd |
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48 / 74 page ![]() 48 Figure 7.14b Fast Read Instruction (QPI Mode) 7.3.3 Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins, DO and DI, instead of just DO. This allows data to be transferred from the ZB25VQ128 at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution. Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in Figure 7.15. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the DI pin should be high-impedance prior to the falling edge of the first data out clock. Figure 7.15 Fast Read Dual Output Instruction Sequence Diagram 7.3.4 Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Dual Output (3Bh) instruction except that data is output on four pins, IO0, IO1, IO2 and IO3. A Quad enable of status Register-2 must be executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from HM25Q128A at four times the rate of standard SPI devices. The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding "dummy" clocks after the 24-bit address as shown in Figure 7.16. The input data during the dummy clocks is "don't care". However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. HM25Q128A |
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