T25S16AFEPR datasheet(43/74 Pages) HMSEMI

43 / 74 page

instruction must be executed before the device will accept the Quad Page Program instruction (Status

"32h" followed by a 24-bit address (A23-0) and at least one data byte, into the IO pins. The CS# pin must be

held low for entire length of the instruction while data is being sent to the device. All other functions of Quad

Page Program are identical to standard Page Program. The Quad Page Program instructions sequence is

shown in Figure 7.7.

Figure 7.7 Quad Page Program Instruction

7.2.3 Sector Erase (SE) (20h)

The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all

1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase

Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and

shifting the instruction code “20h” followed a 24-bit sector address (A23-A0). The Sector Erase instruction

sequence is shown in Figure 7.8.

The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done

the Sector Erase instruction will not be executed. After CS# is driven high, the self-timed Sector Erase

instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase cycle is

in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit.

The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device

is ready to accept other instructions again. After the Sector Erase cycle has finished the Write Enable Latch

(WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the

addressed page is protected by the Block Protect (TB, SEC, BP2, BP1, and BP0) bits (see Status Register

Memory Protection table).

Figure 7.8a Sector Erase Instruction(SPI Mode)

HM25Q128A

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