T25S16AFEPR datasheet(45/74 Pages) HMSEMI

45 / 74 page

The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write

Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register

bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the instruction code

“C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 7.10.

The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase

instruction will not be executed. After CS# is driven high, the self-timed Chip Erase instruction will commence

for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress, the Read Status

Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again.

After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0.

The Chip Erase instruction will not be executed if any page is protected by the Block Protect (SEC, TB, BP2,

BP1, and BP0) bits (see Status Register Memory Protection table).

Figure 7.10 Chip Erase Instruction(SPI or QPI Mode)

7.2.6 Erase / Program Suspend (75h)

The Erase / Program Suspend command allows the system to interrupt a Sector or Block Erase operation,

then read from or program data to any other sector. The Erase / Program Suspend command also allows the

system to interrupt a Page Program operation and then read from any other page or erase any other sector or

block. The Erase / Program Suspend command sequence is shown in Figure 7.11.

The Write Status Registers command (01h, 31h, 11h), and Erase commands (20h, 52h, D8h, C7h, 60h,

44h) are not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase

operation. If written during the Chip Erase operation, the Erase Suspend command is ignored. The Write

Status Registers command (01h, 31h), and Program commands (02h, 32h, 42h) are not allowed during

Program Suspend. Program Suspend is valid during the Page Program or Quad Page Program operation.

The Erase / Program Suspend command 75h will be accepted by the device only if the SUS bit in the

Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program

operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend command will be

ignored by the device. Program or Erase command for the sector that is being suspended will be ignored.

A maximum of time of tSUS (Section 8.5, AC Electrical Characteristics) is required to suspend the erase or

program operation. The BUSY bit in the Status Register will be cleared from 1 to 0 within tSUS and the SUS bit

in the Status Register will be set from 0 to 1 immediately after Erase/Program Suspend. For a previously

resumed Erase/Program operation, it is also required that the Suspend command 75h is not issued earlier

than a minimum of time of tSUS following the preceding Resume command 7Ah.

Unexpected power off during the Erase / Program suspend state will reset the device and release the

suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that

was being suspended may become corrupted. It is recommended for the user to implement system design

techniques to prevent accidental power interruption, provide non-volatile tracking of in process program or

erase commands, and preserve data integrity by evaluating the non-volatile program or erase tracking

information during each system power up in order to identify and repair (re-erase and re-program) any

improperly terminated program or erase operations.

HM25Q128A

T25S16AFEPR bảng dữ liệu(PDF) 45 Page - Shenzhen Huazhimei Semiconductor Co., Ltd