T25S16AFEPR datasheet(59/74 Pages) HMSEMI

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Address

A23-16

A15-8

A7-0

Security Register-1

00h

10h

Byte Address

Security Register-2

00h

20h

Byte Address

Security Register-3

00h

30h

Byte Address

Note:

1. Addresses outside the ranges in the table have undefined results.

The Program Security Register command sequence is shown in Figure 7.34. The Security Register Lock

Bits (LB3:1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set

to 1, the corresponding security register will be permanently locked, and a Program Security Register

command to that register will be ignored.

Figure 7.34 Program Security Registers Instruction

7.5.8 Read Security Registers (48h)

The Read Security Register command is similar to the Fast Read command and allows one or more data

bytes to be sequentially read from one of the three security registers. The command is initiated by driving the

CS# pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and eight

“dummy” clocks into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After

the address is received, and following the eight dummy cycles, the data byte of the addressed memory

location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first.

Locations with address bits A23-A16 not equal to zero, have undefined data. The byte address is

automatically incremented to the next byte address after each byte of data is shifted out. Once the byte

address reaches the last byte of the register (FFh), it will reset to the first byte of the register (00h) and

continue to increase. The command is completed by driving CS# high. The Read Security Register command

sequence is shown in Figure 7.35. If a Read Security Register command is issued while an Erase, Program,

or Write cycle is in process (BUSY=1), the command is ignored and will not have any effects on the current

cycle. The Read Security Register command allows clock rates from DC to a maximum of FR (see Section 8.5,

AC Electrical Characteristics).

Address

A23-16

A15-8

A7-0

Security Register-1

00h

10h

Byte Address

Security Register-2

00h

20h

Byte Address

Security Register-3

00h

30h

Byte Address

Note:

1. Addresses outside the ranges in the table have undefined results.

Figure 7.35 Read Security Registers Instruction

7.5.9 Individual Block/Sector Lock (36h)

The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse

Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be

set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2:0] bits in

HM25Q128A

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