T25S16AFEPR datasheet(52/74 Pages) HMSEMI

52 / 74 page

Figure 7.21 Word Read Quad I/O Instruction(Initial command or previous M5-4 ≠10)

Figure 7.22 Word Read Quad I/O Instruction(Initial command or previous M5-4 =10)

Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode

The Word Read Quad I/O instruction can also be used to access a specific portion within a page by

issuing a “Set Burst with Wrap” (77h) command prior to E7h. The “Set Burst with Wrap” (77h) command can

either enable or disable the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is

enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page.

The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of

the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until CS# is

pulled high to terminate the command.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and

then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read

commands.

The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to

enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around

section within a page. See 7.3.9 for detail descriptions.

7.3.8 Octal Word Read Quad I/O (E3h)

The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction

except that the lower four Address bits (A0, A1 , A2, A3) must equal 0. As a result, the dummy clocks are not

required, which further reduces the instruction overhead allowing even faster random access for code

execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal Word Read

Quad I/O Instruction.

Octal Word Read Quad I/O with “Continuous Read Mode”

The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the

“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.23. The upper

nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through the inclusion

or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However,

the IO pins should be high-impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is

HM25Q128A

T25S16AFEPR bảng dữ liệu(PDF) 52 Page - Shenzhen Huazhimei Semiconductor Co., Ltd