T25S16AFEPR datasheet(51/74 Pages) HMSEMI

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Fast Read Quad I/O (EBh) in QPI Mode

The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 7.19b When QPI

mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction

to accommodate a wide range of applications with different needs for either maximum Fast Read frequency or

minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy

clocks can be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a

Reset instruction is 2. In QPI mode, the “Continuous Read Mode” bits M7-0 are also considered as dummy

clocks. In the default setting, the data output will follow the Continuous Read Mode bits immediately.

“

Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction.

Please refer to the description on previous pages.

“

Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a

read operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch)

instruction must be used. Please refer to 7.5.13 for details.

Figure 7.19b Fast Read Quad I/O Instruction(Initial command or previous M5-4 ≠10,QPI Mode)

7.3.7 Word Read Quad I/O (E7h)

The Word Read Quad I/O (E7h) instruction is similar to the Fast Quad I/O (EBh) instruction except that

the lowest Address bit (A0) must equal to 0 and only two Dummy clocks are required prior to the data output.

The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution

(XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the

Word Read Quad I/O instruction.

Word Read Quad I/O with "Continuous Read Mode"

The Word Read Quad I/O instruction can further reduce instruction overhead through setting the

"Continuous Read Mode" bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.21. The upper

nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or

exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don't care ("X"). However,

the IO pins should be high-impedance prior to the falling edge of the first data out clock.

If the "Continuous Read Mode" bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS#

is raised and then lowered) does not require the E7h instruction code, as shown in Figure 7.22. This reduces

the instruction sequence by eight clocks and allows the read address to be immediately entered after CS# is

asserted low. The "Continuous Read Mode Reset” instruction is also able to reset M7-0 before issuing normal

instructions.

HM25Q128A

T25S16AFEPR bảng dữ liệu(PDF) 51 Page - Shenzhen Huazhimei Semiconductor Co., Ltd