T25S16AFEPR datasheet(41/74 Pages) HMSEMI

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been executed for the device to accept the Write Status Registers Command (Status Register bit WEL must

equal 1). Once write enabled, the command is entered by driving CS# low, sending the instruction code “01h”,

and then writing the Status Register data bytes as illustrated in Figure 7.5.

To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) command must

have been executed prior to the Write Status Registers command (Status Register bit WEL remains 0).

However, SRP1 and LB3, LB2, LB1 cannot be changed because of the OTP protection for these bits. Upon

power-off, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will

be restored when power on again.

To complete the Write Status Registers command, the CS# pin must be driven high after the eighth bit of

a data value is clocked in (CS# must be driven high on an 8-bit boundary). If this is not done the Write Status

Registers command will not be executed.

The Write Status Register instruction allows the Status Register to be written. A Write Enable instruction

must previously have been executed for the device to accept the Write Status Register Instruction (Status

the instruction code “01h”, and then writing the status register data byte as illustrated in Figure 7.5.

During non-volatile Status Register write operation (06h combined with 01h/31h), after CS# is driven high,

the self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics).

While the Write Status Register cycle is in progress, the Read Status Register instruction may still be

accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and

a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status Register

cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.

During volatile Status Register write operation (50h combined with 01h/31h/11h), after CS# is driven high,

the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC

Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.

If CS# is driven high after the eighth clock, the Write Status Register-1 (01h) instruction will only program

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