T25S16AFEPR datasheet(50/74 Pages) HMSEMI

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Fast Read Quad I/O with “Continuous Read Mode”

The Fast Read Quad I/O command can further reduce instruction overhead through setting the

“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.19, Fast Read

Quad I/O Command Sequence (Initial command or previous M5-4≠10). The upper nibble of the (M7-4)

controls the length of the next Fast Read Quad I/O command through the inclusion or exclusion of the first

byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“X”). However, the IO pins should be

high-impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O command (after CS#

is raised and then lowered) does not require the EBh instruction code, as shown in Figure 7.20, Fast Read

Quad I/O Command Sequence (Previous command set M5-4 = 10). This reduces the command sequence by

eight clocks and allows the Read address to be immediately entered after CS# is asserted low. If the

“Continuous Read Mode” bits M5-4 do not equal to (1, 0), the next command (after CS# is raised and then

lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to

input FFh on IO0 for the next instruction (8 clocks), to ensure M4=1 and return the device to normal operation.

Figure 7.19a Fast Read Quad I/O Instruction(Initial command or previous M5-4 ≠10)

Figure 7.20 Fast Read Quad I/O Instruction(Previous command set M5-4 = 10)

Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around”

The Fast Read Quad I/O command can also be used to access a specific portion within a page by issuing

a “Set Burst with Wrap” command prior to EBh. The “Set Burst with Wrap” command can either enable or

disable the “Wrap Around” feature for the following EBh commands. When “Wrap Around” is enabled, the data

being accessed can be limited to 8/16/32/64-byte section of data. The output data starts at the initial address

specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will

wrap around to the beginning boundary automatically until CS# is pulled high to terminate the command.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and

then fill the cache afterwards within a fixed length (8/16/32/64-bytes) of data without issuing multiple read

commands.

The “Set Burst with Wrap” command allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to

enable or disable the “Wrap Around” operation while W6-5 is used to specify the length of the wrap around

section within a page. See Section 7.3.9, Set Burst with Wrap (77h).

HM25Q128A

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