T25S16AFEPR datasheet(26/74 Pages) HMSEMI

26 / 74 page

Status Registers command. LB[3:1] are One Time Programmable (OTP), once it’s set to 1, the corresponding

256-byte Security Register will become read-only permanently.

6.2.10 Quad Enable (QE)

The Quad Enable (QE) bit is a non-volatile read / write bit in the Status Register (SR2[1]) that allows

Quad SPI operation. When the QE bit is set to a 0 state (factory default), the WP# pin and HOLD# / RESET#

are enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and WP# and HOLD# /

RESET# functions are disabled.

Note: If the WP# or HOLD# / RESET# pins are tied directly to the power supply or ground during standard SPI or Dual SPI operation, the

QE bit should never be set to a 1.

6.2.11 HOLD# or RESET# Pin Function (HRSW)

The HRSW bit is used to determine whether HOLD# or RESET# function should be implemented on the

hardware pin for 8-pin packages. When HRSW=0, the pin acts as #HOLD; when HRSW=1, the pin acts as

RESET#. However, HOLD# or RESET# functions are only available when QE=0. If QE is set to 1, the HOLD#

and RESET# functions are disabled, the pin acts as a dedicated data I/O pin.

6.2.12 Output Driver Strength (DRV1, DRV0)

The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.

DRV1, DRV0

Driver Strength

0, 0

50%

0, 1

25%

1, 0

75%(default)

1, 1

100%

6.2.13 High Frequency Enable Bit (HFQ)

The HFQ bit is used to determine whether the device is in Quad High Frequency Mode. When HFQ bit

sets to 1, it means the device is in Quad High Frequency Mode, when HFQ bit sets 0 (default), it means the

device is not in Quad High Frequency Mode. This Mode allows pre-charge of internal charge pump, so the

voltages required for accessing the flash memory array are readily available for Quad read. After the HFQ is

executed, the device will maintain a slightly higher standby current (ICC8) than standard SPI operation.

6.2.14 Write Protect Selection (WPS)

The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the device will

use the combination of CMP, SEC, TB, BP[2:0] bits to protect a specific area of the memory array. When

WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The default

value for all Individual Block Lock bits is 1 upon device power on or after reset.

6.2.15 Latency Control (LC)

Status Register-3 provides bits (SR3[1:0]) to select the number of read latency cycles used in each Fast

Read command(only in SPI mode). The Read Data command is not affected by the latency code. The binary

value of this field selects from 2,4,6 latency cycles. The default is 0 to provide backward compatibility to

legacy devices. The Latency Control bits may be set to select a number of read cycles optimized for the

frequency in use. If the number of latency cycles is not sufficient for the operating frequency, invalid data will

be read.

HM25Q128A

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